forked from Minki/linux
phy: qcom-qmp-pcie: drop support for non-PCIe PHY types
Drop remaining support for PHY types other than PCIe. Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220607213203.2819885-16-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Dmitry Baryshkov
Vinod Koul
parent
b2bac0f095
commit
da07a06b90
@ -1832,7 +1832,6 @@ static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy)
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struct qcom_qmp *qmp = qphy->qmp;
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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void __iomem *serdes = qphy->serdes;
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const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
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const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
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int serdes_tbl_num = cfg->serdes_tbl_num;
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int ret;
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@ -1842,35 +1841,6 @@ static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy)
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qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
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cfg->serdes_tbl_num_sec);
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if (cfg->type == PHY_TYPE_DP) {
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switch (dp_opts->link_rate) {
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case 1620:
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qcom_qmp_phy_pcie_configure(serdes, cfg->regs,
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cfg->serdes_tbl_rbr,
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cfg->serdes_tbl_rbr_num);
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break;
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case 2700:
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qcom_qmp_phy_pcie_configure(serdes, cfg->regs,
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cfg->serdes_tbl_hbr,
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cfg->serdes_tbl_hbr_num);
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break;
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case 5400:
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qcom_qmp_phy_pcie_configure(serdes, cfg->regs,
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cfg->serdes_tbl_hbr2,
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cfg->serdes_tbl_hbr2_num);
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break;
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case 8100:
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qcom_qmp_phy_pcie_configure(serdes, cfg->regs,
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cfg->serdes_tbl_hbr3,
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cfg->serdes_tbl_hbr3_num);
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break;
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default:
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/* Other link rates aren't supported */
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return -EINVAL;
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}
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}
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if (cfg->has_phy_com_ctrl) {
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void __iomem *status;
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unsigned int mask, val;
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@ -1894,32 +1864,6 @@ static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy)
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return 0;
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}
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static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
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{
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const struct phy_configure_opts_dp *dp_opts = &opts->dp;
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struct qmp_phy *qphy = phy_get_drvdata(phy);
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
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if (qphy->dp_opts.set_voltages) {
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cfg->configure_dp_tx(qphy);
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qphy->dp_opts.set_voltages = 0;
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}
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return 0;
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}
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static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
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{
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struct qmp_phy *qphy = phy_get_drvdata(phy);
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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if (cfg->calibrate_dp_phy)
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return cfg->calibrate_dp_phy(qphy);
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return 0;
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}
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static int qcom_qmp_phy_pcie_com_init(struct qmp_phy *qphy)
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{
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struct qcom_qmp *qmp = qphy->qmp;
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@ -2089,9 +2033,6 @@ static int qcom_qmp_phy_pcie_init(struct phy *phy)
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if (ret)
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return ret;
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if (cfg->type == PHY_TYPE_DP)
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cfg->dp_aux_init(qphy);
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return 0;
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}
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@ -2142,10 +2083,6 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy)
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cfg->tx_tbl_num_sec, 2);
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}
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/* Configure special DP tx tunings */
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if (cfg->type == PHY_TYPE_DP)
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cfg->configure_dp_tx(qphy);
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qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs,
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cfg->rx_tbl, cfg->rx_tbl_num, 1);
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if (cfg->rx_tbl_sec)
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@ -2161,15 +2098,10 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy)
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cfg->rx_tbl_num_sec, 2);
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}
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/* Configure link rate, swing, etc. */
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if (cfg->type == PHY_TYPE_DP) {
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cfg->configure_dp_phy(qphy);
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} else {
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qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
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if (cfg->pcs_tbl_sec)
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qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
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cfg->pcs_tbl_num_sec);
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}
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qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
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if (cfg->pcs_tbl_sec)
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qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
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cfg->pcs_tbl_num_sec);
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ret = reset_control_deassert(qmp->ufs_reset);
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if (ret)
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@ -2185,36 +2117,28 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy)
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* Pull out PHY from POWER DOWN state.
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* This is active low enable signal to power-down PHY.
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*/
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if(cfg->type == PHY_TYPE_PCIE)
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qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
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qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
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if (cfg->has_pwrdn_delay)
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usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
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if (cfg->type != PHY_TYPE_DP) {
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/* Pull PHY out of reset state */
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if (!cfg->no_pcs_sw_reset)
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qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
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/* start SerDes and Phy-Coding-Sublayer */
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qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
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/* Pull PHY out of reset state */
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if (!cfg->no_pcs_sw_reset)
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qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
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/* start SerDes and Phy-Coding-Sublayer */
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qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
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if (cfg->type == PHY_TYPE_UFS) {
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status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
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mask = PCS_READY;
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ready = PCS_READY;
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} else {
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status = pcs + cfg->regs[QPHY_PCS_STATUS];
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mask = cfg->phy_status;
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ready = 0;
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}
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status = pcs + cfg->regs[QPHY_PCS_STATUS];
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mask = cfg->phy_status;
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ready = 0;
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ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
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PHY_INIT_COMPLETE_TIMEOUT);
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if (ret) {
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dev_err(qmp->dev, "phy initialization timed-out\n");
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goto err_disable_pipe_clk;
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}
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ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
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PHY_INIT_COMPLETE_TIMEOUT);
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if (ret) {
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dev_err(qmp->dev, "phy initialization timed-out\n");
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goto err_disable_pipe_clk;
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}
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return 0;
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err_disable_pipe_clk:
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@ -2233,25 +2157,20 @@ static int qcom_qmp_phy_pcie_power_off(struct phy *phy)
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clk_disable_unprepare(qphy->pipe_clk);
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if (cfg->type == PHY_TYPE_DP) {
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/* Assert DP PHY power down */
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writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
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/* PHY reset */
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if (!cfg->no_pcs_sw_reset)
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qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
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/* stop SerDes and Phy-Coding-Sublayer */
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qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
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/* Put PHY into POWER DOWN state: active low */
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if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
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qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
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cfg->pwrdn_ctrl);
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} else {
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/* PHY reset */
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if (!cfg->no_pcs_sw_reset)
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qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
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/* stop SerDes and Phy-Coding-Sublayer */
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qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
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/* Put PHY into POWER DOWN state: active low */
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if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
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qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
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cfg->pwrdn_ctrl);
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} else {
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qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
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cfg->pwrdn_ctrl);
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}
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qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
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cfg->pwrdn_ctrl);
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}
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return 0;
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@ -2305,112 +2224,6 @@ static int qcom_qmp_phy_pcie_set_mode(struct phy *phy,
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return 0;
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}
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static void qcom_qmp_phy_pcie_enable_autonomous_mode(struct qmp_phy *qphy)
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{
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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void __iomem *pcs = qphy->pcs;
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void __iomem *pcs_misc = qphy->pcs_misc;
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u32 intr_mask;
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if (qphy->mode == PHY_MODE_USB_HOST_SS ||
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qphy->mode == PHY_MODE_USB_DEVICE_SS)
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intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
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else
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intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
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/* Clear any pending interrupts status */
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qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
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/* Writing 1 followed by 0 clears the interrupt */
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qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
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qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
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ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
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/* Enable required PHY autonomous mode interrupts */
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qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
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/* Enable i/o clamp_n for autonomous mode */
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if (pcs_misc)
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qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
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}
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static void qcom_qmp_phy_pcie_disable_autonomous_mode(struct qmp_phy *qphy)
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{
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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void __iomem *pcs = qphy->pcs;
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void __iomem *pcs_misc = qphy->pcs_misc;
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/* Disable i/o clamp_n on resume for normal mode */
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if (pcs_misc)
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qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
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qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
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ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
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qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
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/* Writing 1 followed by 0 clears the interrupt */
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qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
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}
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static int __maybe_unused qcom_qmp_phy_pcie_runtime_suspend(struct device *dev)
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{
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struct qcom_qmp *qmp = dev_get_drvdata(dev);
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struct qmp_phy *qphy = qmp->phys[0];
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
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/* Supported only for USB3 PHY and luckily USB3 is the first phy */
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if (cfg->type != PHY_TYPE_USB3)
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return 0;
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if (!qmp->init_count) {
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dev_vdbg(dev, "PHY not initialized, bailing out\n");
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return 0;
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}
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qcom_qmp_phy_pcie_enable_autonomous_mode(qphy);
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clk_disable_unprepare(qphy->pipe_clk);
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clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
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return 0;
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}
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static int __maybe_unused qcom_qmp_phy_pcie_runtime_resume(struct device *dev)
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{
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struct qcom_qmp *qmp = dev_get_drvdata(dev);
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struct qmp_phy *qphy = qmp->phys[0];
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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int ret = 0;
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dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
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/* Supported only for USB3 PHY and luckily USB3 is the first phy */
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if (cfg->type != PHY_TYPE_USB3)
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return 0;
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if (!qmp->init_count) {
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dev_vdbg(dev, "PHY not initialized, bailing out\n");
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return 0;
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}
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ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
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if (ret)
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return ret;
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ret = clk_prepare_enable(qphy->pipe_clk);
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if (ret) {
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dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
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clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
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return ret;
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}
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qcom_qmp_phy_pcie_disable_autonomous_mode(qphy);
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return 0;
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}
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static int qcom_qmp_phy_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
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{
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struct qcom_qmp *qmp = dev_get_drvdata(dev);
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@ -2528,223 +2341,13 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
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return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
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}
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/*
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* Display Port PLL driver block diagram for branch clocks
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*
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* +------------------------------+
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* | DP_VCO_CLK |
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* | |
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* | +-------------------+ |
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* | | (DP PLL/VCO) | |
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* | +---------+---------+ |
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* | v |
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* | +----------+-----------+ |
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* | | hsclk_divsel_clk_src | |
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* | +----------+-----------+ |
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* +------------------------------+
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* |
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* +---------<---------v------------>----------+
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* | |
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* +--------v----------------+ |
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* | dp_phy_pll_link_clk | |
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* | link_clk | |
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* +--------+----------------+ |
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* | |
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* | |
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* v v
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* Input to DISPCC block |
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* for link clk, crypto clk |
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* and interface clock |
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* |
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* |
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* +--------<------------+-----------------+---<---+
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* | | |
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* +----v---------+ +--------v-----+ +--------v------+
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* | vco_divided | | vco_divided | | vco_divided |
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* | _clk_src | | _clk_src | | _clk_src |
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* | | | | | |
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* |divsel_six | | divsel_two | | divsel_four |
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* +-------+------+ +-----+--------+ +--------+------+
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* | | |
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* v---->----------v-------------<------v
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* |
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* +----------+-----------------+
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* | dp_phy_pll_vco_div_clk |
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* +---------+------------------+
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* |
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* v
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* Input to DISPCC block
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* for DP pixel clock
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*
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*/
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static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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switch (req->rate) {
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case 1620000000UL / 2:
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case 2700000000UL / 2:
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/* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
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return 0;
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default:
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return -EINVAL;
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}
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}
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static unsigned long
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qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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const struct qmp_phy_dp_clks *dp_clks;
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const struct qmp_phy *qphy;
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const struct phy_configure_opts_dp *dp_opts;
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dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
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qphy = dp_clks->qphy;
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dp_opts = &qphy->dp_opts;
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switch (dp_opts->link_rate) {
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case 1620:
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return 1620000000UL / 2;
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case 2700:
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return 2700000000UL / 2;
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case 5400:
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return 5400000000UL / 4;
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case 8100:
|
||||
return 8100000000UL / 6;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
|
||||
.determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
|
||||
.recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
|
||||
};
|
||||
|
||||
static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
switch (req->rate) {
|
||||
case 162000000:
|
||||
case 270000000:
|
||||
case 540000000:
|
||||
case 810000000:
|
||||
return 0;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned long
|
||||
qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
||||
{
|
||||
const struct qmp_phy_dp_clks *dp_clks;
|
||||
const struct qmp_phy *qphy;
|
||||
const struct phy_configure_opts_dp *dp_opts;
|
||||
|
||||
dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
|
||||
qphy = dp_clks->qphy;
|
||||
dp_opts = &qphy->dp_opts;
|
||||
|
||||
switch (dp_opts->link_rate) {
|
||||
case 1620:
|
||||
case 2700:
|
||||
case 5400:
|
||||
case 8100:
|
||||
return dp_opts->link_rate * 100000;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
|
||||
.determine_rate = qcom_qmp_dp_link_clk_determine_rate,
|
||||
.recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
|
||||
};
|
||||
|
||||
static struct clk_hw *
|
||||
qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
|
||||
{
|
||||
struct qmp_phy_dp_clks *dp_clks = data;
|
||||
unsigned int idx = clkspec->args[0];
|
||||
|
||||
if (idx >= 2) {
|
||||
pr_err("%s: invalid index %u\n", __func__, idx);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
if (idx == 0)
|
||||
return &dp_clks->dp_link_hw;
|
||||
|
||||
return &dp_clks->dp_pixel_hw;
|
||||
}
|
||||
|
||||
static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
|
||||
struct device_node *np)
|
||||
{
|
||||
struct clk_init_data init = { };
|
||||
struct qmp_phy_dp_clks *dp_clks;
|
||||
char name[64];
|
||||
int ret;
|
||||
|
||||
dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
|
||||
if (!dp_clks)
|
||||
return -ENOMEM;
|
||||
|
||||
dp_clks->qphy = qphy;
|
||||
qphy->dp_clks = dp_clks;
|
||||
|
||||
snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
|
||||
init.ops = &qcom_qmp_dp_link_clk_ops;
|
||||
init.name = name;
|
||||
dp_clks->dp_link_hw.init = &init;
|
||||
ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
|
||||
init.ops = &qcom_qmp_dp_pixel_clk_ops;
|
||||
init.name = name;
|
||||
dp_clks->dp_pixel_hw.init = &init;
|
||||
ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* Roll a devm action because the clock provider is the child node, but
|
||||
* the child node is not actually a device.
|
||||
*/
|
||||
return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
|
||||
}
|
||||
|
||||
static const struct phy_ops qcom_qmp_phy_pcie_gen_ops = {
|
||||
static const struct phy_ops qcom_qmp_phy_pcie_ops = {
|
||||
.init = qcom_qmp_phy_pcie_enable,
|
||||
.exit = qcom_qmp_phy_pcie_disable,
|
||||
.set_mode = qcom_qmp_phy_pcie_set_mode,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static const struct phy_ops qcom_qmp_phy_pcie_dp_ops = {
|
||||
.init = qcom_qmp_phy_pcie_init,
|
||||
.configure = qcom_qmp_dp_phy_configure,
|
||||
.power_on = qcom_qmp_phy_pcie_power_on,
|
||||
.calibrate = qcom_qmp_dp_phy_calibrate,
|
||||
.power_off = qcom_qmp_phy_pcie_power_off,
|
||||
.exit = qcom_qmp_phy_pcie_exit,
|
||||
.set_mode = qcom_qmp_phy_pcie_set_mode,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
|
||||
.power_on = qcom_qmp_phy_pcie_enable,
|
||||
.power_off = qcom_qmp_phy_pcie_disable,
|
||||
.set_mode = qcom_qmp_phy_pcie_set_mode,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static void qcom_qmp_reset_control_put(void *data)
|
||||
{
|
||||
reset_control_put(data);
|
||||
@ -2757,7 +2360,6 @@ int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id,
|
||||
struct qcom_qmp *qmp = dev_get_drvdata(dev);
|
||||
struct phy *generic_phy;
|
||||
struct qmp_phy *qphy;
|
||||
const struct phy_ops *ops;
|
||||
char prop_name[MAX_PROP_NAME];
|
||||
int ret;
|
||||
|
||||
@ -2850,14 +2452,7 @@ int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id,
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
|
||||
ops = &qcom_qmp_pcie_ufs_ops;
|
||||
else if (cfg->type == PHY_TYPE_DP)
|
||||
ops = &qcom_qmp_phy_pcie_dp_ops;
|
||||
else
|
||||
ops = &qcom_qmp_phy_pcie_gen_ops;
|
||||
|
||||
generic_phy = devm_phy_create(dev, np, ops);
|
||||
generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_ops);
|
||||
if (IS_ERR(generic_phy)) {
|
||||
ret = PTR_ERR(generic_phy);
|
||||
dev_err(dev, "failed to create qphy %d\n", ret);
|
||||
@ -2915,11 +2510,6 @@ static const struct of_device_id qcom_qmp_phy_pcie_of_match_table[] = {
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, qcom_qmp_phy_pcie_of_match_table);
|
||||
|
||||
static const struct dev_pm_ops qcom_qmp_phy_pcie_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(qcom_qmp_phy_pcie_runtime_suspend,
|
||||
qcom_qmp_phy_pcie_runtime_resume, NULL)
|
||||
};
|
||||
|
||||
static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct qcom_qmp *qmp;
|
||||
@ -2927,12 +2517,7 @@ static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev)
|
||||
struct device_node *child;
|
||||
struct phy_provider *phy_provider;
|
||||
void __iomem *serdes;
|
||||
void __iomem *usb_serdes;
|
||||
void __iomem *dp_serdes = NULL;
|
||||
const struct qmp_phy_combo_cfg *combo_cfg = NULL;
|
||||
const struct qmp_phy_cfg *cfg = NULL;
|
||||
const struct qmp_phy_cfg *usb_cfg = NULL;
|
||||
const struct qmp_phy_cfg *dp_cfg = NULL;
|
||||
int num, id, expected_phys;
|
||||
int ret;
|
||||
|
||||
@ -2949,28 +2534,18 @@ static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev)
|
||||
return -EINVAL;
|
||||
|
||||
/* per PHY serdes; usually located at base address */
|
||||
usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
|
||||
serdes = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(serdes))
|
||||
return PTR_ERR(serdes);
|
||||
|
||||
/* per PHY dp_com; if PHY has dp_com control block */
|
||||
if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
|
||||
if (cfg->has_phy_dp_com_ctrl) {
|
||||
qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
|
||||
if (IS_ERR(qmp->dp_com))
|
||||
return PTR_ERR(qmp->dp_com);
|
||||
}
|
||||
|
||||
if (combo_cfg) {
|
||||
/* Only two serdes for combo PHY */
|
||||
dp_serdes = devm_platform_ioremap_resource(pdev, 2);
|
||||
if (IS_ERR(dp_serdes))
|
||||
return PTR_ERR(dp_serdes);
|
||||
|
||||
dp_cfg = combo_cfg->dp_cfg;
|
||||
expected_phys = 2;
|
||||
} else {
|
||||
expected_phys = cfg->nlanes;
|
||||
}
|
||||
expected_phys = cfg->nlanes;
|
||||
|
||||
mutex_init(&qmp->phy_mutex);
|
||||
|
||||
@ -3009,14 +2584,6 @@ static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev)
|
||||
|
||||
id = 0;
|
||||
for_each_available_child_of_node(dev->of_node, child) {
|
||||
if (of_node_name_eq(child, "dp-phy")) {
|
||||
cfg = dp_cfg;
|
||||
serdes = dp_serdes;
|
||||
} else if (of_node_name_eq(child, "usb3-phy")) {
|
||||
cfg = usb_cfg;
|
||||
serdes = usb_serdes;
|
||||
}
|
||||
|
||||
/* Create per-lane phy */
|
||||
ret = qcom_qmp_phy_pcie_create(dev, child, id, serdes, cfg);
|
||||
if (ret) {
|
||||
@ -3029,21 +2596,13 @@ static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev)
|
||||
* Register the pipe clock provided by phy.
|
||||
* See function description to see details of this pipe clock.
|
||||
*/
|
||||
if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
|
||||
ret = phy_pipe_clk_register(qmp, child);
|
||||
if (ret) {
|
||||
dev_err(qmp->dev,
|
||||
"failed to register pipe clock source\n");
|
||||
goto err_node_put;
|
||||
}
|
||||
} else if (cfg->type == PHY_TYPE_DP) {
|
||||
ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
|
||||
if (ret) {
|
||||
dev_err(qmp->dev,
|
||||
"failed to register DP clock source\n");
|
||||
goto err_node_put;
|
||||
}
|
||||
ret = phy_pipe_clk_register(qmp, child);
|
||||
if (ret) {
|
||||
dev_err(qmp->dev,
|
||||
"failed to register pipe clock source\n");
|
||||
goto err_node_put;
|
||||
}
|
||||
|
||||
id++;
|
||||
}
|
||||
|
||||
@ -3065,7 +2624,6 @@ static struct platform_driver qcom_qmp_phy_pcie_driver = {
|
||||
.probe = qcom_qmp_phy_pcie_probe,
|
||||
.driver = {
|
||||
.name = "qcom-qmp-pcie-phy",
|
||||
.pm = &qcom_qmp_phy_pcie_pm_ops,
|
||||
.of_match_table = qcom_qmp_phy_pcie_of_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user