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drm/i915: Ensure cache flushes prior to doing CS flips

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Synchronising to an object active on the same ring is a no-op, for the
benefit of execbuffer scheduler. However, for CS flips this means that
we can forgo checking whether the last write request of the object is
actually queued and more importantly whether the cache flush for the
write was emitted.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Chris Wilson 2015-04-27 13:41:15 +01:00 committed by Daniel Vetter
parent 2e2f351dbf
commit d94b5030d2
1 changed files with 6 additions and 0 deletions
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6
drivers/gpu/drm/i915/intel_display.c
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@ -11040,6 +11040,12 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
i915_gem_request_assign(&work->flip_queued_req,
obj->last_write_req);
} else {
if (obj->last_write_req) {
ret = i915_gem_check_olr(obj->last_write_req);
if (ret)
goto cleanup_unpin;
}
ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
page_flip_flags);
if (ret)