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mlxsw: reg: Add Switch Port Egress VLAN EtherType Register

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SPEVET configures which EtherType to push at egress for packets incoming
through a local port for which 'SPVID.egr_et_set' is set.

The next patches will use SPEVET to configure EtherType 0x88A8 and
0x8100 for local ports member in 802.1ad and 802.1q bridges,
respectively. This allows using dual VxLAN bridges (802.1d and 802.1ad at
the same time).

Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Amit Cohen 2021-03-17 12:35:24 +02:00 committed by David S. Miller
parent 1b35293b7a
commit d8f4da73ce
1 changed files with 36 additions and 0 deletions
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36
drivers/net/ethernet/mellanox/mlxsw/reg.h
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@ -2088,6 +2088,41 @@ static inline void mlxsw_reg_spvc_pack(char *payload, u8 local_port, bool et1,
mlxsw_reg_spvc_et0_set(payload, et0);
}
/* SPEVET - Switch Port Egress VLAN EtherType
* ------------------------------------------
* The switch port egress VLAN EtherType configures which EtherType to push at
* egress for packets incoming through a local port for which 'SPVID.egr_et_set'
* is set.
*/
#define MLXSW_REG_SPEVET_ID 0x202A
#define MLXSW_REG_SPEVET_LEN 0x08
MLXSW_REG_DEFINE(spevet, MLXSW_REG_SPEVET_ID, MLXSW_REG_SPEVET_LEN);
/* reg_spevet_local_port
* Egress Local port number.
* Not supported to CPU port.
* Access: Index
*/
MLXSW_ITEM32(reg, spevet, local_port, 0x00, 16, 8);
/* reg_spevet_et_vlan
* Egress EtherType VLAN to push when SPVID.egr_et_set field set for the packet:
* 0: ether_type0 - (default)
* 1: ether_type1
* 2: ether_type2
* Access: RW
*/
MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2);
static inline void mlxsw_reg_spevet_pack(char *payload, u8 local_port,
u8 et_vlan)
{
MLXSW_REG_ZERO(spevet, payload);
mlxsw_reg_spevet_local_port_set(payload, local_port);
mlxsw_reg_spevet_et_vlan_set(payload, et_vlan);
}
/* CWTP - Congetion WRED ECN TClass Profile
* ----------------------------------------
* Configures the profiles for queues of egress port and traffic class
@ -12026,6 +12061,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
MLXSW_REG(sfmr),
MLXSW_REG(spvmlr),
MLXSW_REG(spvc),
MLXSW_REG(spevet),
MLXSW_REG(cwtp),
MLXSW_REG(cwtpm),
MLXSW_REG(pgcr),