forked from Minki/linux
staging: octeon-usb: delete unused cvmx_usbnx_usbp_ctl_status definitions
cvmx_usbnx_usbp_ctl_status was multiplied for different OCTEONS and all those definitions are unused. Delete them. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Aaro Koskinen
Greg Kroah-Hartman
parent
9f627100b9
commit
d8d8e148fd
@ -498,388 +498,6 @@ union cvmx_usbnx_usbp_ctl_status {
|
||||
uint64_t tdata_in : 8;
|
||||
uint64_t ate_reset : 1;
|
||||
} s;
|
||||
/**
|
||||
* struct cvmx_usbnx_usbp_ctl_status_cn30xx
|
||||
* @bist_done: PHY Bist Done.
|
||||
* Asserted at the end of the PHY BIST sequence.
|
||||
* @bist_err: PHY Bist Error.
|
||||
* Indicates an internal error was detected during
|
||||
* the BIST sequence.
|
||||
* @tdata_out: PHY Test Data Out.
|
||||
* Presents either internaly generated signals or
|
||||
* test register contents, based upon the value of
|
||||
* test_data_out_sel.
|
||||
* @dma_bmode: When set to 1 the L2C DMA address will be updated
|
||||
* with byte-counts between packets. When set to 0
|
||||
* the L2C DMA address is incremented to the next
|
||||
* 4-byte aligned address after adding byte-count.
|
||||
* @usbc_end: Bigendian input to the USB Core. This should be
|
||||
* set to '0' for operation.
|
||||
* @usbp_bist: PHY, This is cleared '0' to run BIST on the USBP.
|
||||
* @tclk: PHY Test Clock, used to load TDATA_IN to the USBP.
|
||||
* @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY.
|
||||
* This signal enables the pull-down resistance on
|
||||
* the D+ line. '1' pull down-resistance is connected
|
||||
* to D+/ '0' pull down resistance is not connected
|
||||
* to D+. When an A/B device is acting as a host
|
||||
* (downstream-facing port), dp_pulldown and
|
||||
* dm_pulldown are enabled. This must not toggle
|
||||
* during normal opeartion.
|
||||
* @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY.
|
||||
* This signal enables the pull-down resistance on
|
||||
* the D- line. '1' pull down-resistance is connected
|
||||
* to D-. '0' pull down resistance is not connected
|
||||
* to D-. When an A/B device is acting as a host
|
||||
* (downstream-facing port), dp_pulldown and
|
||||
* dm_pulldown are enabled. This must not toggle
|
||||
* during normal opeartion.
|
||||
* @hst_mode: When '0' the USB is acting as HOST, when '1'
|
||||
* USB is acting as device. This field needs to be
|
||||
* set while the USB is in reset.
|
||||
* @tuning: Transmitter Tuning for High-Speed Operation.
|
||||
* Tunes the current supply and rise/fall output
|
||||
* times for high-speed operation.
|
||||
* [20:19] == 11: Current supply increased
|
||||
* approximately 9%
|
||||
* [20:19] == 10: Current supply increased
|
||||
* approximately 4.5%
|
||||
* [20:19] == 01: Design default.
|
||||
* [20:19] == 00: Current supply decreased
|
||||
* approximately 4.5%
|
||||
* [22:21] == 11: Rise and fall times are increased.
|
||||
* [22:21] == 10: Design default.
|
||||
* [22:21] == 01: Rise and fall times are decreased.
|
||||
* [22:21] == 00: Rise and fall times are decreased
|
||||
* further as compared to the 01 setting.
|
||||
* @tx_bs_enh: Transmit Bit Stuffing on [15:8].
|
||||
* Enables or disables bit stuffing on data[15:8]
|
||||
* when bit-stuffing is enabled.
|
||||
* @tx_bs_en: Transmit Bit Stuffing on [7:0].
|
||||
* Enables or disables bit stuffing on data[7:0]
|
||||
* when bit-stuffing is enabled.
|
||||
* @loop_enb: PHY Loopback Test Enable.
|
||||
* '1': During data transmission the receive is
|
||||
* enabled.
|
||||
* '0': During data transmission the receive is
|
||||
* disabled.
|
||||
* Must be '0' for normal operation.
|
||||
* @vtest_enb: Analog Test Pin Enable.
|
||||
* '1' The PHY's analog_test pin is enabled for the
|
||||
* input and output of applicable analog test signals.
|
||||
* '0' THe analog_test pin is disabled.
|
||||
* @bist_enb: Built-In Self Test Enable.
|
||||
* Used to activate BIST in the PHY.
|
||||
* @tdata_sel: Test Data Out Select.
|
||||
* '1' test_data_out[3:0] (PHY) register contents
|
||||
* are output. '0' internaly generated signals are
|
||||
* output.
|
||||
* @taddr_in: Mode Address for Test Interface.
|
||||
* Specifies the register address for writing to or
|
||||
* reading from the PHY test interface register.
|
||||
* @tdata_in: Internal Testing Register Input Data and Select
|
||||
* This is a test bus. Data is present on [3:0],
|
||||
* and its corresponding select (enable) is present
|
||||
* on bits [7:4].
|
||||
* @ate_reset: Reset input from automatic test equipment.
|
||||
* This is a test signal. When the USB Core is
|
||||
* powered up (not in Susned Mode), an automatic
|
||||
* tester can use this to disable phy_clock and
|
||||
* free_clk, then re-eanable them with an aligned
|
||||
* phase.
|
||||
* '1': The phy_clk and free_clk outputs are
|
||||
* disabled. "0": The phy_clock and free_clk outputs
|
||||
* are available within a specific period after the
|
||||
* de-assertion.
|
||||
*/
|
||||
struct cvmx_usbnx_usbp_ctl_status_cn30xx {
|
||||
uint64_t reserved_38_63 : 26;
|
||||
uint64_t bist_done : 1;
|
||||
uint64_t bist_err : 1;
|
||||
uint64_t tdata_out : 4;
|
||||
uint64_t reserved_30_31 : 2;
|
||||
uint64_t dma_bmode : 1;
|
||||
uint64_t usbc_end : 1;
|
||||
uint64_t usbp_bist : 1;
|
||||
uint64_t tclk : 1;
|
||||
uint64_t dp_pulld : 1;
|
||||
uint64_t dm_pulld : 1;
|
||||
uint64_t hst_mode : 1;
|
||||
uint64_t tuning : 4;
|
||||
uint64_t tx_bs_enh : 1;
|
||||
uint64_t tx_bs_en : 1;
|
||||
uint64_t loop_enb : 1;
|
||||
uint64_t vtest_enb : 1;
|
||||
uint64_t bist_enb : 1;
|
||||
uint64_t tdata_sel : 1;
|
||||
uint64_t taddr_in : 4;
|
||||
uint64_t tdata_in : 8;
|
||||
uint64_t ate_reset : 1;
|
||||
} cn30xx;
|
||||
/**
|
||||
* struct cvmx_usbnx_usbp_ctl_status_cn50xx
|
||||
* @txrisetune: HS Transmitter Rise/Fall Time Adjustment
|
||||
* @txvreftune: HS DC Voltage Level Adjustment
|
||||
* @txfslstune: FS/LS Source Impedence Adjustment
|
||||
* @txhsxvtune: Transmitter High-Speed Crossover Adjustment
|
||||
* @sqrxtune: Squelch Threshold Adjustment
|
||||
* @compdistune: Disconnect Threshold Adjustment
|
||||
* @otgtune: VBUS Valid Threshold Adjustment
|
||||
* @otgdisable: OTG Block Disable
|
||||
* @portreset: Per_Port Reset
|
||||
* @drvvbus: Drive VBUS
|
||||
* @lsbist: Low-Speed BIST Enable.
|
||||
* @fsbist: Full-Speed BIST Enable.
|
||||
* @hsbist: High-Speed BIST Enable.
|
||||
* @bist_done: PHY Bist Done.
|
||||
* Asserted at the end of the PHY BIST sequence.
|
||||
* @bist_err: PHY Bist Error.
|
||||
* Indicates an internal error was detected during
|
||||
* the BIST sequence.
|
||||
* @tdata_out: PHY Test Data Out.
|
||||
* Presents either internaly generated signals or
|
||||
* test register contents, based upon the value of
|
||||
* test_data_out_sel.
|
||||
* @txpreemphasistune: HS Transmitter Pre-Emphasis Enable
|
||||
* @dma_bmode: When set to 1 the L2C DMA address will be updated
|
||||
* with byte-counts between packets. When set to 0
|
||||
* the L2C DMA address is incremented to the next
|
||||
* 4-byte aligned address after adding byte-count.
|
||||
* @usbc_end: Bigendian input to the USB Core. This should be
|
||||
* set to '0' for operation.
|
||||
* @usbp_bist: PHY, This is cleared '0' to run BIST on the USBP.
|
||||
* @tclk: PHY Test Clock, used to load TDATA_IN to the USBP.
|
||||
* @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY.
|
||||
* This signal enables the pull-down resistance on
|
||||
* the D+ line. '1' pull down-resistance is connected
|
||||
* to D+/ '0' pull down resistance is not connected
|
||||
* to D+. When an A/B device is acting as a host
|
||||
* (downstream-facing port), dp_pulldown and
|
||||
* dm_pulldown are enabled. This must not toggle
|
||||
* during normal opeartion.
|
||||
* @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY.
|
||||
* This signal enables the pull-down resistance on
|
||||
* the D- line. '1' pull down-resistance is connected
|
||||
* to D-. '0' pull down resistance is not connected
|
||||
* to D-. When an A/B device is acting as a host
|
||||
* (downstream-facing port), dp_pulldown and
|
||||
* dm_pulldown are enabled. This must not toggle
|
||||
* during normal opeartion.
|
||||
* @hst_mode: When '0' the USB is acting as HOST, when '1'
|
||||
* USB is acting as device. This field needs to be
|
||||
* set while the USB is in reset.
|
||||
* @tx_bs_enh: Transmit Bit Stuffing on [15:8].
|
||||
* Enables or disables bit stuffing on data[15:8]
|
||||
* when bit-stuffing is enabled.
|
||||
* @tx_bs_en: Transmit Bit Stuffing on [7:0].
|
||||
* Enables or disables bit stuffing on data[7:0]
|
||||
* when bit-stuffing is enabled.
|
||||
* @loop_enb: PHY Loopback Test Enable.
|
||||
* '1': During data transmission the receive is
|
||||
* enabled.
|
||||
* '0': During data transmission the receive is
|
||||
* disabled.
|
||||
* Must be '0' for normal operation.
|
||||
* @vtest_enb: Analog Test Pin Enable.
|
||||
* '1' The PHY's analog_test pin is enabled for the
|
||||
* input and output of applicable analog test signals.
|
||||
* '0' THe analog_test pin is disabled.
|
||||
* @bist_enb: Built-In Self Test Enable.
|
||||
* Used to activate BIST in the PHY.
|
||||
* @tdata_sel: Test Data Out Select.
|
||||
* '1' test_data_out[3:0] (PHY) register contents
|
||||
* are output. '0' internaly generated signals are
|
||||
* output.
|
||||
* @taddr_in: Mode Address for Test Interface.
|
||||
* Specifies the register address for writing to or
|
||||
* reading from the PHY test interface register.
|
||||
* @tdata_in: Internal Testing Register Input Data and Select
|
||||
* This is a test bus. Data is present on [3:0],
|
||||
* and its corresponding select (enable) is present
|
||||
* on bits [7:4].
|
||||
* @ate_reset: Reset input from automatic test equipment.
|
||||
* This is a test signal. When the USB Core is
|
||||
* powered up (not in Susned Mode), an automatic
|
||||
* tester can use this to disable phy_clock and
|
||||
* free_clk, then re-eanable them with an aligned
|
||||
* phase.
|
||||
* '1': The phy_clk and free_clk outputs are
|
||||
* disabled. "0": The phy_clock and free_clk outputs
|
||||
* are available within a specific period after the
|
||||
* de-assertion.
|
||||
*/
|
||||
struct cvmx_usbnx_usbp_ctl_status_cn50xx {
|
||||
uint64_t txrisetune : 1;
|
||||
uint64_t txvreftune : 4;
|
||||
uint64_t txfslstune : 4;
|
||||
uint64_t txhsxvtune : 2;
|
||||
uint64_t sqrxtune : 3;
|
||||
uint64_t compdistune : 3;
|
||||
uint64_t otgtune : 3;
|
||||
uint64_t otgdisable : 1;
|
||||
uint64_t portreset : 1;
|
||||
uint64_t drvvbus : 1;
|
||||
uint64_t lsbist : 1;
|
||||
uint64_t fsbist : 1;
|
||||
uint64_t hsbist : 1;
|
||||
uint64_t bist_done : 1;
|
||||
uint64_t bist_err : 1;
|
||||
uint64_t tdata_out : 4;
|
||||
uint64_t reserved_31_31 : 1;
|
||||
uint64_t txpreemphasistune : 1;
|
||||
uint64_t dma_bmode : 1;
|
||||
uint64_t usbc_end : 1;
|
||||
uint64_t usbp_bist : 1;
|
||||
uint64_t tclk : 1;
|
||||
uint64_t dp_pulld : 1;
|
||||
uint64_t dm_pulld : 1;
|
||||
uint64_t hst_mode : 1;
|
||||
uint64_t reserved_19_22 : 4;
|
||||
uint64_t tx_bs_enh : 1;
|
||||
uint64_t tx_bs_en : 1;
|
||||
uint64_t loop_enb : 1;
|
||||
uint64_t vtest_enb : 1;
|
||||
uint64_t bist_enb : 1;
|
||||
uint64_t tdata_sel : 1;
|
||||
uint64_t taddr_in : 4;
|
||||
uint64_t tdata_in : 8;
|
||||
uint64_t ate_reset : 1;
|
||||
} cn50xx;
|
||||
/**
|
||||
* struct cvmx_usbnx_usbp_ctl_status_cn52xx
|
||||
* @txrisetune: HS Transmitter Rise/Fall Time Adjustment
|
||||
* @txvreftune: HS DC Voltage Level Adjustment
|
||||
* @txfslstune: FS/LS Source Impedence Adjustment
|
||||
* @txhsxvtune: Transmitter High-Speed Crossover Adjustment
|
||||
* @sqrxtune: Squelch Threshold Adjustment
|
||||
* @compdistune: Disconnect Threshold Adjustment
|
||||
* @otgtune: VBUS Valid Threshold Adjustment
|
||||
* @otgdisable: OTG Block Disable
|
||||
* @portreset: Per_Port Reset
|
||||
* @drvvbus: Drive VBUS
|
||||
* @lsbist: Low-Speed BIST Enable.
|
||||
* @fsbist: Full-Speed BIST Enable.
|
||||
* @hsbist: High-Speed BIST Enable.
|
||||
* @bist_done: PHY Bist Done.
|
||||
* Asserted at the end of the PHY BIST sequence.
|
||||
* @bist_err: PHY Bist Error.
|
||||
* Indicates an internal error was detected during
|
||||
* the BIST sequence.
|
||||
* @tdata_out: PHY Test Data Out.
|
||||
* Presents either internaly generated signals or
|
||||
* test register contents, based upon the value of
|
||||
* test_data_out_sel.
|
||||
* @siddq: Drives the USBP (USB-PHY) SIDDQ input.
|
||||
* Normally should be set to zero.
|
||||
* When customers have no intent to use USB PHY
|
||||
* interface, they should:
|
||||
* - still provide 3.3V to USB_VDD33, and
|
||||
* - tie USB_REXT to 3.3V supply, and
|
||||
* - set USBN*_USBP_CTL_STATUS[SIDDQ]=1
|
||||
* @txpreemphasistune: HS Transmitter Pre-Emphasis Enable
|
||||
* @dma_bmode: When set to 1 the L2C DMA address will be updated
|
||||
* with byte-counts between packets. When set to 0
|
||||
* the L2C DMA address is incremented to the next
|
||||
* 4-byte aligned address after adding byte-count.
|
||||
* @usbc_end: Bigendian input to the USB Core. This should be
|
||||
* set to '0' for operation.
|
||||
* @usbp_bist: PHY, This is cleared '0' to run BIST on the USBP.
|
||||
* @tclk: PHY Test Clock, used to load TDATA_IN to the USBP.
|
||||
* @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY.
|
||||
* This signal enables the pull-down resistance on
|
||||
* the D+ line. '1' pull down-resistance is connected
|
||||
* to D+/ '0' pull down resistance is not connected
|
||||
* to D+. When an A/B device is acting as a host
|
||||
* (downstream-facing port), dp_pulldown and
|
||||
* dm_pulldown are enabled. This must not toggle
|
||||
* during normal opeartion.
|
||||
* @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY.
|
||||
* This signal enables the pull-down resistance on
|
||||
* the D- line. '1' pull down-resistance is connected
|
||||
* to D-. '0' pull down resistance is not connected
|
||||
* to D-. When an A/B device is acting as a host
|
||||
* (downstream-facing port), dp_pulldown and
|
||||
* dm_pulldown are enabled. This must not toggle
|
||||
* during normal opeartion.
|
||||
* @hst_mode: When '0' the USB is acting as HOST, when '1'
|
||||
* USB is acting as device. This field needs to be
|
||||
* set while the USB is in reset.
|
||||
* @tx_bs_enh: Transmit Bit Stuffing on [15:8].
|
||||
* Enables or disables bit stuffing on data[15:8]
|
||||
* when bit-stuffing is enabled.
|
||||
* @tx_bs_en: Transmit Bit Stuffing on [7:0].
|
||||
* Enables or disables bit stuffing on data[7:0]
|
||||
* when bit-stuffing is enabled.
|
||||
* @loop_enb: PHY Loopback Test Enable.
|
||||
* '1': During data transmission the receive is
|
||||
* enabled.
|
||||
* '0': During data transmission the receive is
|
||||
* disabled.
|
||||
* Must be '0' for normal operation.
|
||||
* @vtest_enb: Analog Test Pin Enable.
|
||||
* '1' The PHY's analog_test pin is enabled for the
|
||||
* input and output of applicable analog test signals.
|
||||
* '0' THe analog_test pin is disabled.
|
||||
* @bist_enb: Built-In Self Test Enable.
|
||||
* Used to activate BIST in the PHY.
|
||||
* @tdata_sel: Test Data Out Select.
|
||||
* '1' test_data_out[3:0] (PHY) register contents
|
||||
* are output. '0' internaly generated signals are
|
||||
* output.
|
||||
* @taddr_in: Mode Address for Test Interface.
|
||||
* Specifies the register address for writing to or
|
||||
* reading from the PHY test interface register.
|
||||
* @tdata_in: Internal Testing Register Input Data and Select
|
||||
* This is a test bus. Data is present on [3:0],
|
||||
* and its corresponding select (enable) is present
|
||||
* on bits [7:4].
|
||||
* @ate_reset: Reset input from automatic test equipment.
|
||||
* This is a test signal. When the USB Core is
|
||||
* powered up (not in Susned Mode), an automatic
|
||||
* tester can use this to disable phy_clock and
|
||||
* free_clk, then re-eanable them with an aligned
|
||||
* phase.
|
||||
* '1': The phy_clk and free_clk outputs are
|
||||
* disabled. "0": The phy_clock and free_clk outputs
|
||||
* are available within a specific period after the
|
||||
* de-assertion.
|
||||
*/
|
||||
struct cvmx_usbnx_usbp_ctl_status_cn52xx {
|
||||
uint64_t txrisetune : 1;
|
||||
uint64_t txvreftune : 4;
|
||||
uint64_t txfslstune : 4;
|
||||
uint64_t txhsxvtune : 2;
|
||||
uint64_t sqrxtune : 3;
|
||||
uint64_t compdistune : 3;
|
||||
uint64_t otgtune : 3;
|
||||
uint64_t otgdisable : 1;
|
||||
uint64_t portreset : 1;
|
||||
uint64_t drvvbus : 1;
|
||||
uint64_t lsbist : 1;
|
||||
uint64_t fsbist : 1;
|
||||
uint64_t hsbist : 1;
|
||||
uint64_t bist_done : 1;
|
||||
uint64_t bist_err : 1;
|
||||
uint64_t tdata_out : 4;
|
||||
uint64_t siddq : 1;
|
||||
uint64_t txpreemphasistune : 1;
|
||||
uint64_t dma_bmode : 1;
|
||||
uint64_t usbc_end : 1;
|
||||
uint64_t usbp_bist : 1;
|
||||
uint64_t tclk : 1;
|
||||
uint64_t dp_pulld : 1;
|
||||
uint64_t dm_pulld : 1;
|
||||
uint64_t hst_mode : 1;
|
||||
uint64_t reserved_19_22 : 4;
|
||||
uint64_t tx_bs_enh : 1;
|
||||
uint64_t tx_bs_en : 1;
|
||||
uint64_t loop_enb : 1;
|
||||
uint64_t vtest_enb : 1;
|
||||
uint64_t bist_enb : 1;
|
||||
uint64_t tdata_sel : 1;
|
||||
uint64_t taddr_in : 4;
|
||||
uint64_t tdata_in : 8;
|
||||
uint64_t ate_reset : 1;
|
||||
} cn52xx;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user