forked from Minki/linux
[ARM] tegra: Add clock support
v2: fixes from Russell King: - include linux/io.h instead of asm/io.h - fix whitespace in Kconfig - Use spin_lock_init to initialize lock - Return -ENOSYS instead of BUG for unimplemented clock ops - Use proper return values in tegra2 clock ops additional changes: - Rename some clocks to match dev_ids - add rate propagation - add debugfs entries - add support for clock listed in clk_lookup under multiple dev_ids v3: - Replace per-clock locking with global clock lock - Autodetect clock state on init - Let clock dividers pick next lower possible frequency - Add support for clock init tables - Minor bug fixes - Fix checkpatch issues Signed-off-by: Colin Cross <ccross@android.com>
This commit is contained in:
parent
5ad36c5f0e
commit
d861196163
@ -568,6 +568,7 @@ config ARCH_TEGRA
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select GENERIC_CLOCKEVENTS
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select GENERIC_GPIO
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select HAVE_CLK
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select COMMON_CLKDEV
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select ARCH_HAS_BARRIERS if CACHE_L2X0
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help
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This enables support for NVIDIA Tegra based systems (Tegra APX,
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@ -1,3 +1,5 @@
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obj-y += common.o
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obj-y += io.o
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obj-y += irq.o
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obj-y += clock.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
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488
arch/arm/mach-tegra/clock.c
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488
arch/arm/mach-tegra/clock.c
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@ -0,0 +1,488 @@
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/*
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*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/list.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/debugfs.h>
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#include <linux/slab.h>
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#include <linux/seq_file.h>
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#include <asm/clkdev.h>
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#include "clock.h"
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static LIST_HEAD(clocks);
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static DEFINE_SPINLOCK(clock_lock);
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struct clk *tegra_get_clock_by_name(const char *name)
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{
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struct clk *c;
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struct clk *ret = NULL;
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unsigned long flags;
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spin_lock_irqsave(&clock_lock, flags);
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list_for_each_entry(c, &clocks, node) {
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if (strcmp(c->name, name) == 0) {
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ret = c;
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break;
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}
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}
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spin_unlock_irqrestore(&clock_lock, flags);
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return ret;
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}
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int clk_reparent(struct clk *c, struct clk *parent)
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{
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pr_debug("%s: %s\n", __func__, c->name);
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if (c->refcnt && c->parent)
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clk_disable_locked(c->parent);
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c->parent = parent;
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if (c->refcnt && c->parent)
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clk_enable_locked(c->parent);
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list_del(&c->sibling);
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list_add_tail(&c->sibling, &parent->children);
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return 0;
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}
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static void propagate_rate(struct clk *c)
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{
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struct clk *clkp;
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pr_debug("%s: %s\n", __func__, c->name);
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list_for_each_entry(clkp, &c->children, sibling) {
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pr_debug(" %s\n", clkp->name);
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if (clkp->ops->recalculate_rate)
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clkp->ops->recalculate_rate(clkp);
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propagate_rate(clkp);
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}
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}
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void clk_init(struct clk *c)
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{
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unsigned long flags;
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spin_lock_irqsave(&clock_lock, flags);
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INIT_LIST_HEAD(&c->children);
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INIT_LIST_HEAD(&c->sibling);
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if (c->ops && c->ops->init)
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c->ops->init(c);
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list_add(&c->node, &clocks);
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if (c->parent)
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list_add_tail(&c->sibling, &c->parent->children);
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spin_unlock_irqrestore(&clock_lock, flags);
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}
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int clk_enable_locked(struct clk *c)
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{
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int ret;
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pr_debug("%s: %s\n", __func__, c->name);
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if (c->refcnt == 0) {
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if (c->parent) {
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ret = clk_enable_locked(c->parent);
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if (ret)
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return ret;
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}
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if (c->ops && c->ops->enable) {
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ret = c->ops->enable(c);
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if (ret) {
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if (c->parent)
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clk_disable_locked(c->parent);
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return ret;
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}
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c->state = ON;
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#ifdef CONFIG_DEBUG_FS
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c->set = 1;
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#endif
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}
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}
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c->refcnt++;
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return 0;
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}
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int clk_enable(struct clk *c)
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{
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int ret;
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unsigned long flags;
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spin_lock_irqsave(&clock_lock, flags);
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ret = clk_enable_locked(c);
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spin_unlock_irqrestore(&clock_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable_locked(struct clk *c)
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{
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pr_debug("%s: %s\n", __func__, c->name);
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if (c->refcnt == 0) {
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WARN(1, "Attempting to disable clock %s with refcnt 0", c->name);
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return;
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}
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if (c->refcnt == 1) {
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if (c->ops && c->ops->disable)
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c->ops->disable(c);
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if (c->parent)
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clk_disable_locked(c->parent);
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c->state = OFF;
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}
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c->refcnt--;
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}
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void clk_disable(struct clk *c)
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{
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unsigned long flags;
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spin_lock_irqsave(&clock_lock, flags);
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clk_disable_locked(c);
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spin_unlock_irqrestore(&clock_lock, flags);
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}
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EXPORT_SYMBOL(clk_disable);
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int clk_set_parent_locked(struct clk *c, struct clk *parent)
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{
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int ret;
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pr_debug("%s: %s\n", __func__, c->name);
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if (!c->ops || !c->ops->set_parent)
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return -ENOSYS;
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ret = c->ops->set_parent(c, parent);
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if (ret)
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return ret;
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propagate_rate(c);
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return 0;
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}
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int clk_set_parent(struct clk *c, struct clk *parent)
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{
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int ret;
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unsigned long flags;
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spin_lock_irqsave(&clock_lock, flags);
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ret = clk_set_parent_locked(c, parent);
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spin_unlock_irqrestore(&clock_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(clk_set_parent);
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struct clk *clk_get_parent(struct clk *c)
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{
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return c->parent;
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}
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EXPORT_SYMBOL(clk_get_parent);
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int clk_set_rate(struct clk *c, unsigned long rate)
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{
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int ret = 0;
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unsigned long flags;
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spin_lock_irqsave(&clock_lock, flags);
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pr_debug("%s: %s\n", __func__, c->name);
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if (c->ops && c->ops->set_rate)
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ret = c->ops->set_rate(c, rate);
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else
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ret = -ENOSYS;
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propagate_rate(c);
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spin_unlock_irqrestore(&clock_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(clk_set_rate);
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unsigned long clk_get_rate(struct clk *c)
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{
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unsigned long flags;
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unsigned long ret;
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spin_lock_irqsave(&clock_lock, flags);
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pr_debug("%s: %s\n", __func__, c->name);
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ret = c->rate;
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spin_unlock_irqrestore(&clock_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(clk_get_rate);
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static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
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{
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struct clk *c;
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struct clk *p;
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int ret = 0;
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c = tegra_get_clock_by_name(table->name);
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if (!c) {
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pr_warning("Unable to initialize clock %s\n",
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table->name);
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return -ENODEV;
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}
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if (table->parent) {
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p = tegra_get_clock_by_name(table->parent);
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if (!p) {
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pr_warning("Unable to find parent %s of clock %s\n",
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table->parent, table->name);
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return -ENODEV;
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}
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if (c->parent != p) {
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ret = clk_set_parent(c, p);
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if (ret) {
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pr_warning("Unable to set parent %s of clock %s: %d\n",
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table->parent, table->name, ret);
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return -EINVAL;
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}
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}
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}
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if (table->rate && table->rate != clk_get_rate(c)) {
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ret = clk_set_rate(c, table->rate);
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if (ret) {
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pr_warning("Unable to set clock %s to rate %lu: %d\n",
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table->name, table->rate, ret);
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return -EINVAL;
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}
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}
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if (table->enabled) {
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ret = clk_enable(c);
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if (ret) {
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pr_warning("Unable to enable clock %s: %d\n",
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table->name, ret);
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return -EINVAL;
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}
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}
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return 0;
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}
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void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
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{
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for (; table->name; table++)
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tegra_clk_init_one_from_table(table);
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}
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EXPORT_SYMBOL(tegra_clk_init_from_table);
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void tegra_periph_reset_deassert(struct clk *c)
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{
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tegra2_periph_reset_deassert(c);
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}
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EXPORT_SYMBOL(tegra_periph_reset_deassert);
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void tegra_periph_reset_assert(struct clk *c)
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{
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tegra2_periph_reset_assert(c);
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}
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EXPORT_SYMBOL(tegra_periph_reset_assert);
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int __init tegra_init_clock(void)
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{
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tegra2_init_clocks();
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return 0;
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}
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#ifdef CONFIG_DEBUG_FS
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static struct dentry *clk_debugfs_root;
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static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level)
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{
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struct clk *child;
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struct clk *safe;
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const char *state = "uninit";
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char div[5] = {0};
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if (c->state == ON)
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state = "on";
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else if (c->state == OFF)
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state = "off";
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if (c->mul != 0 && c->div != 0) {
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BUG_ON(c->mul > 2);
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if (c->mul > c->div)
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snprintf(div, sizeof(div), "x%d", c->mul / c->div);
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else
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snprintf(div, sizeof(div), "%d%s", c->div / c->mul,
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(c->div % c->mul) ? ".5" : "");
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}
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seq_printf(s, "%*s%-*s %-6s %-3d %-5s %-10lu\n",
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level * 3 + 1, c->set ? "" : "*",
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30 - level * 3, c->name,
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state, c->refcnt, div, c->rate);
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list_for_each_entry_safe(child, safe, &c->children, sibling) {
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clock_tree_show_one(s, child, level + 1);
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}
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}
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static int clock_tree_show(struct seq_file *s, void *data)
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{
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struct clk *c;
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unsigned long flags;
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seq_printf(s, " clock state ref div rate \n");
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seq_printf(s, "-----------------------------------------------------------\n");
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spin_lock_irqsave(&clock_lock, flags);
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list_for_each_entry(c, &clocks, node)
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if (c->parent == NULL)
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clock_tree_show_one(s, c, 0);
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spin_unlock_irqrestore(&clock_lock, flags);
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return 0;
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}
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static int clock_tree_open(struct inode *inode, struct file *file)
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{
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return single_open(file, clock_tree_show, inode->i_private);
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}
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static const struct file_operations clock_tree_fops = {
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.open = clock_tree_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int possible_parents_show(struct seq_file *s, void *data)
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{
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struct clk *c = s->private;
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int i;
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for (i = 0; c->inputs[i].input; i++) {
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char *first = (i == 0) ? "" : " ";
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seq_printf(s, "%s%s", first, c->inputs[i].input->name);
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}
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seq_printf(s, "\n");
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return 0;
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}
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static int possible_parents_open(struct inode *inode, struct file *file)
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{
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return single_open(file, possible_parents_show, inode->i_private);
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}
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static const struct file_operations possible_parents_fops = {
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.open = possible_parents_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int clk_debugfs_register_one(struct clk *c)
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{
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struct dentry *d, *child, *child_tmp;
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d = debugfs_create_dir(c->name, clk_debugfs_root);
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if (!d)
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return -ENOMEM;
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c->dent = d;
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d = debugfs_create_u8("refcnt", S_IRUGO, c->dent, (u8 *)&c->refcnt);
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if (!d)
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goto err_out;
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d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
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if (!d)
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goto err_out;
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d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
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if (!d)
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goto err_out;
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if (c->inputs) {
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d = debugfs_create_file("possible_parents", S_IRUGO, c->dent,
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c, &possible_parents_fops);
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if (!d)
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goto err_out;
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}
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return 0;
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err_out:
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d = c->dent;
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list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
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debugfs_remove(child);
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debugfs_remove(c->dent);
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return -ENOMEM;
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}
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static int clk_debugfs_register(struct clk *c)
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{
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int err;
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struct clk *pa = c->parent;
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if (pa && !pa->dent) {
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err = clk_debugfs_register(pa);
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if (err)
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return err;
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}
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if (!c->dent) {
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err = clk_debugfs_register_one(c);
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if (err)
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return err;
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}
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return 0;
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}
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|
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static int __init clk_debugfs_init(void)
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{
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struct clk *c;
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struct dentry *d;
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int err = -ENOMEM;
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d = debugfs_create_dir("clock", NULL);
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if (!d)
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return -ENOMEM;
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clk_debugfs_root = d;
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d = debugfs_create_file("clock_tree", S_IRUGO, clk_debugfs_root, NULL,
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&clock_tree_fops);
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if (!d)
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goto err_out;
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list_for_each_entry(c, &clocks, node) {
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err = clk_debugfs_register(c);
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if (err)
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goto err_out;
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}
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return 0;
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err_out:
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debugfs_remove_recursive(clk_debugfs_root);
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return err;
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}
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late_initcall(clk_debugfs_init);
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#endif
|
147
arch/arm/mach-tegra/clock.h
Normal file
147
arch/arm/mach-tegra/clock.h
Normal file
@ -0,0 +1,147 @@
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/*
|
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* arch/arm/mach-tegra/include/mach/clock.h
|
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*
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
*
|
||||
* Author:
|
||||
* Colin Cross <ccross@google.com>
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MACH_TEGRA_CLOCK_H
|
||||
#define __MACH_TEGRA_CLOCK_H
|
||||
|
||||
#include <linux/list.h>
|
||||
#include <asm/clkdev.h>
|
||||
|
||||
#define DIV_BUS (1 << 0)
|
||||
#define DIV_U71 (1 << 1)
|
||||
#define DIV_U71_FIXED (1 << 2)
|
||||
#define DIV_2 (1 << 3)
|
||||
#define PLL_FIXED (1 << 4)
|
||||
#define PLL_HAS_CPCON (1 << 5)
|
||||
#define MUX (1 << 6)
|
||||
#define PLLD (1 << 7)
|
||||
#define PERIPH_NO_RESET (1 << 8)
|
||||
#define PERIPH_NO_ENB (1 << 9)
|
||||
#define PERIPH_EMC_ENB (1 << 10)
|
||||
#define PERIPH_MANUAL_RESET (1 << 11)
|
||||
#define PLL_ALT_MISC_REG (1 << 12)
|
||||
#define ENABLE_ON_INIT (1 << 28)
|
||||
|
||||
struct clk;
|
||||
|
||||
struct clk_mux_sel {
|
||||
struct clk *input;
|
||||
u32 value;
|
||||
};
|
||||
|
||||
struct clk_pll_table {
|
||||
unsigned long input_rate;
|
||||
unsigned long output_rate;
|
||||
u16 n;
|
||||
u16 m;
|
||||
u8 p;
|
||||
u8 cpcon;
|
||||
};
|
||||
|
||||
struct clk_ops {
|
||||
void (*init)(struct clk *);
|
||||
int (*enable)(struct clk *);
|
||||
void (*disable)(struct clk *);
|
||||
void (*recalc)(struct clk *);
|
||||
int (*set_parent)(struct clk *, struct clk *);
|
||||
int (*set_rate)(struct clk *, unsigned long);
|
||||
unsigned long (*get_rate)(struct clk *);
|
||||
long (*round_rate)(struct clk *, unsigned long);
|
||||
unsigned long (*recalculate_rate)(struct clk *);
|
||||
};
|
||||
|
||||
enum clk_state {
|
||||
UNINITIALIZED = 0,
|
||||
ON,
|
||||
OFF,
|
||||
};
|
||||
|
||||
struct clk {
|
||||
/* node for master clocks list */
|
||||
struct list_head node;
|
||||
struct list_head children; /* list of children */
|
||||
struct list_head sibling; /* node for children */
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
struct dentry *dent;
|
||||
struct dentry *parent_dent;
|
||||
#endif
|
||||
struct clk_ops *ops;
|
||||
struct clk *parent;
|
||||
struct clk_lookup lookup;
|
||||
unsigned long rate;
|
||||
u32 flags;
|
||||
u32 refcnt;
|
||||
const char *name;
|
||||
u32 reg;
|
||||
u32 reg_shift;
|
||||
unsigned int clk_num;
|
||||
enum clk_state state;
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
bool set;
|
||||
#endif
|
||||
|
||||
/* PLL */
|
||||
unsigned long input_min;
|
||||
unsigned long input_max;
|
||||
unsigned long cf_min;
|
||||
unsigned long cf_max;
|
||||
unsigned long vco_min;
|
||||
unsigned long vco_max;
|
||||
u32 m;
|
||||
u32 n;
|
||||
u32 p;
|
||||
u32 cpcon;
|
||||
const struct clk_pll_table *pll_table;
|
||||
|
||||
/* DIV */
|
||||
u32 div;
|
||||
u32 mul;
|
||||
|
||||
/* MUX */
|
||||
const struct clk_mux_sel *inputs;
|
||||
u32 sel;
|
||||
u32 reg_mask;
|
||||
};
|
||||
|
||||
|
||||
struct clk_duplicate {
|
||||
const char *name;
|
||||
struct clk_lookup lookup;
|
||||
};
|
||||
|
||||
struct tegra_clk_init_table {
|
||||
const char *name;
|
||||
const char *parent;
|
||||
unsigned long rate;
|
||||
bool enabled;
|
||||
};
|
||||
|
||||
void tegra2_init_clocks(void);
|
||||
void tegra2_periph_reset_deassert(struct clk *c);
|
||||
void tegra2_periph_reset_assert(struct clk *c);
|
||||
void clk_init(struct clk *clk);
|
||||
struct clk *tegra_get_clock_by_name(const char *name);
|
||||
unsigned long clk_measure_input_freq(void);
|
||||
void clk_disable_locked(struct clk *c);
|
||||
int clk_enable_locked(struct clk *c);
|
||||
int clk_set_parent_locked(struct clk *c, struct clk *parent);
|
||||
int clk_reparent(struct clk *c, struct clk *parent);
|
||||
void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
|
||||
|
||||
#endif
|
@ -25,6 +25,21 @@
|
||||
#include <mach/iomap.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "clock.h"
|
||||
|
||||
static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
|
||||
/* name parent rate enabled */
|
||||
{ "clk_m", NULL, 0, true },
|
||||
{ "pll_p", "clk_m", 216000000, true },
|
||||
{ "pll_p_out1", "pll_p", 28800000, true },
|
||||
{ "pll_p_out2", "pll_p", 48000000, true },
|
||||
{ "pll_p_out3", "pll_p", 72000000, true },
|
||||
{ "pll_p_out4", "pll_p", 108000000, true },
|
||||
{ "sys", "pll_p_out4", 108000000, true },
|
||||
{ "hclk", "sys", 108000000, true },
|
||||
{ "pclk", "hclk", 54000000, true },
|
||||
{ NULL, NULL, 0, 0},
|
||||
};
|
||||
|
||||
void __init tegra_init_cache(void)
|
||||
{
|
||||
@ -40,5 +55,7 @@ void __init tegra_init_cache(void)
|
||||
|
||||
void __init tegra_common_init(void)
|
||||
{
|
||||
tegra_init_clock();
|
||||
tegra_clk_init_from_table(common_clk_init_table);
|
||||
tegra_init_cache();
|
||||
}
|
||||
|
26
arch/arm/mach-tegra/include/mach/clk.h
Normal file
26
arch/arm/mach-tegra/include/mach/clk.h
Normal file
@ -0,0 +1,26 @@
|
||||
/*
|
||||
* arch/arm/mach-tegra/include/mach/clk.h
|
||||
*
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
*
|
||||
* Author:
|
||||
* Erik Gilling <konkers@google.com>
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MACH_CLK_H
|
||||
#define __MACH_CLK_H
|
||||
|
||||
void tegra_periph_reset_deassert(struct clk *c);
|
||||
void tegra_periph_reset_assert(struct clk *c);
|
||||
|
||||
#endif
|
32
arch/arm/mach-tegra/include/mach/clkdev.h
Normal file
32
arch/arm/mach-tegra/include/mach/clkdev.h
Normal file
@ -0,0 +1,32 @@
|
||||
/*
|
||||
* arch/arm/mach-tegra/include/mach/clkdev.h
|
||||
*
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
*
|
||||
* Author:
|
||||
* Colin Cross <ccross@google.com>
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MACH_CLKDEV_H
|
||||
#define __MACH_CLKDEV_H
|
||||
|
||||
static inline int __clk_get(struct clk *clk)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static inline void __clk_put(struct clk *clk)
|
||||
{
|
||||
}
|
||||
|
||||
#endif
|
1359
arch/arm/mach-tegra/tegra2_clocks.c
Normal file
1359
arch/arm/mach-tegra/tegra2_clocks.c
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user