forked from Minki/linux
drm/i915/gvt: Move common workload preparation into prepare_workload()
Move common workload preparation into prepare_workload() in scheduler.c, as they are not specific to execlist emulation. Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
This commit is contained in:
Zhi Wang
Zhenyu Wang
parent
497aa3f5e3
commit
d8235b5e55
@ -361,110 +361,6 @@ static int emulate_execlist_schedule_in(struct intel_vgpu_execlist *execlist,
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#define get_desc_from_elsp_dwords(ed, i) \
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((struct execlist_ctx_descriptor_format *)&((ed)->data[i * 2]))
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static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
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{
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const int gmadr_bytes = workload->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
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struct intel_shadow_bb_entry *entry_obj;
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/* pin the gem object to ggtt */
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list_for_each_entry(entry_obj, &workload->shadow_bb, list) {
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struct i915_vma *vma;
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vma = i915_gem_object_ggtt_pin(entry_obj->obj, NULL, 0, 4, 0);
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if (IS_ERR(vma)) {
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return PTR_ERR(vma);
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}
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/* FIXME: we are not tracking our pinned VMA leaving it
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* up to the core to fix up the stray pin_count upon
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* free.
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*/
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/* update the relocate gma with shadow batch buffer*/
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entry_obj->bb_start_cmd_va[1] = i915_ggtt_offset(vma);
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if (gmadr_bytes == 8)
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entry_obj->bb_start_cmd_va[2] = 0;
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}
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return 0;
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}
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static int update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
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{
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struct intel_vgpu_workload *workload = container_of(wa_ctx,
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struct intel_vgpu_workload,
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wa_ctx);
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int ring_id = workload->ring_id;
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struct intel_vgpu_submission *s = &workload->vgpu->submission;
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struct i915_gem_context *shadow_ctx = s->shadow_ctx;
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struct drm_i915_gem_object *ctx_obj =
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shadow_ctx->engine[ring_id].state->obj;
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struct execlist_ring_context *shadow_ring_context;
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struct page *page;
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page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
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shadow_ring_context = kmap_atomic(page);
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shadow_ring_context->bb_per_ctx_ptr.val =
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(shadow_ring_context->bb_per_ctx_ptr.val &
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(~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma;
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shadow_ring_context->rcs_indirect_ctx.val =
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(shadow_ring_context->rcs_indirect_ctx.val &
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(~INDIRECT_CTX_ADDR_MASK)) | wa_ctx->indirect_ctx.shadow_gma;
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kunmap_atomic(shadow_ring_context);
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return 0;
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}
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static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
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{
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struct i915_vma *vma;
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unsigned char *per_ctx_va =
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(unsigned char *)wa_ctx->indirect_ctx.shadow_va +
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wa_ctx->indirect_ctx.size;
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if (wa_ctx->indirect_ctx.size == 0)
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return 0;
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vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL,
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0, CACHELINE_BYTES, 0);
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if (IS_ERR(vma)) {
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return PTR_ERR(vma);
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}
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/* FIXME: we are not tracking our pinned VMA leaving it
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* up to the core to fix up the stray pin_count upon
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* free.
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*/
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wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma);
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wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1);
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memset(per_ctx_va, 0, CACHELINE_BYTES);
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update_wa_ctx_2_shadow_ctx(wa_ctx);
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return 0;
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}
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static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
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{
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/* release all the shadow batch buffer */
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if (!list_empty(&workload->shadow_bb)) {
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struct intel_shadow_bb_entry *entry_obj =
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list_first_entry(&workload->shadow_bb,
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struct intel_shadow_bb_entry,
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list);
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struct intel_shadow_bb_entry *temp;
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list_for_each_entry_safe(entry_obj, temp, &workload->shadow_bb,
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list) {
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i915_gem_object_unpin_map(entry_obj->obj);
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i915_gem_object_put(entry_obj->obj);
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list_del(&entry_obj->list);
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kfree(entry_obj);
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}
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}
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}
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static int prepare_execlist_workload(struct intel_vgpu_workload *workload)
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{
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struct intel_vgpu *vgpu = workload->vgpu;
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@ -473,36 +369,6 @@ static int prepare_execlist_workload(struct intel_vgpu_workload *workload)
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int ring_id = workload->ring_id;
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int ret;
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ret = intel_vgpu_pin_mm(workload->shadow_mm);
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if (ret) {
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gvt_vgpu_err("fail to vgpu pin mm\n");
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goto out;
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}
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ret = intel_vgpu_sync_oos_pages(workload->vgpu);
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if (ret) {
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gvt_vgpu_err("fail to vgpu sync oos pages\n");
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goto err_unpin_mm;
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}
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ret = intel_vgpu_flush_post_shadow(workload->vgpu);
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if (ret) {
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gvt_vgpu_err("fail to flush post shadow\n");
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goto err_unpin_mm;
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}
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ret = prepare_shadow_batch_buffer(workload);
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if (ret) {
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gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n");
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goto err_unpin_mm;
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}
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ret = prepare_shadow_wa_ctx(&workload->wa_ctx);
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if (ret) {
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gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n");
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goto err_shadow_batch;
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}
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if (!workload->emulate_schedule_in)
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return 0;
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@ -510,18 +376,11 @@ static int prepare_execlist_workload(struct intel_vgpu_workload *workload)
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ctx[1] = *get_desc_from_elsp_dwords(&workload->elsp_dwords, 1);
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ret = emulate_execlist_schedule_in(&s->execlist[ring_id], ctx);
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if (!ret)
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goto out;
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else
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if (ret) {
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gvt_vgpu_err("fail to emulate execlist schedule in\n");
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release_shadow_wa_ctx(&workload->wa_ctx);
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err_shadow_batch:
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release_shadow_batch_buffer(workload);
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err_unpin_mm:
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intel_vgpu_unpin_mm(workload->shadow_mm);
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out:
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return ret;
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return ret;
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}
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return 0;
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}
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static int complete_execlist_workload(struct intel_vgpu_workload *workload)
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@ -538,11 +397,6 @@ static int complete_execlist_workload(struct intel_vgpu_workload *workload)
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gvt_dbg_el("complete workload %p status %d\n", workload,
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workload->status);
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if (!workload->status) {
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release_shadow_batch_buffer(workload);
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release_shadow_wa_ctx(&workload->wa_ctx);
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}
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if (workload->status || (vgpu->resetting_eng & ENGINE_MASK(ring_id))) {
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/* if workload->status is not successful means HW GPU
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* has occurred GPU hang or something wrong with i915/GVT,
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@ -325,13 +325,157 @@ err_scan:
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return ret;
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}
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static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
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{
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struct intel_gvt *gvt = workload->vgpu->gvt;
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const int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
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struct intel_shadow_bb_entry *entry_obj;
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/* pin the gem object to ggtt */
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list_for_each_entry(entry_obj, &workload->shadow_bb, list) {
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struct i915_vma *vma;
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vma = i915_gem_object_ggtt_pin(entry_obj->obj, NULL, 0, 4, 0);
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if (IS_ERR(vma))
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return PTR_ERR(vma);
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/* FIXME: we are not tracking our pinned VMA leaving it
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* up to the core to fix up the stray pin_count upon
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* free.
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*/
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/* update the relocate gma with shadow batch buffer*/
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entry_obj->bb_start_cmd_va[1] = i915_ggtt_offset(vma);
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if (gmadr_bytes == 8)
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entry_obj->bb_start_cmd_va[2] = 0;
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}
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return 0;
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}
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static int update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
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{
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struct intel_vgpu_workload *workload = container_of(wa_ctx,
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struct intel_vgpu_workload,
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wa_ctx);
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int ring_id = workload->ring_id;
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struct intel_vgpu_submission *s = &workload->vgpu->submission;
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struct i915_gem_context *shadow_ctx = s->shadow_ctx;
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struct drm_i915_gem_object *ctx_obj =
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shadow_ctx->engine[ring_id].state->obj;
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struct execlist_ring_context *shadow_ring_context;
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struct page *page;
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page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
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shadow_ring_context = kmap_atomic(page);
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shadow_ring_context->bb_per_ctx_ptr.val =
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(shadow_ring_context->bb_per_ctx_ptr.val &
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(~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma;
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shadow_ring_context->rcs_indirect_ctx.val =
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(shadow_ring_context->rcs_indirect_ctx.val &
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(~INDIRECT_CTX_ADDR_MASK)) | wa_ctx->indirect_ctx.shadow_gma;
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kunmap_atomic(shadow_ring_context);
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return 0;
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}
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static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
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{
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struct i915_vma *vma;
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unsigned char *per_ctx_va =
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(unsigned char *)wa_ctx->indirect_ctx.shadow_va +
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wa_ctx->indirect_ctx.size;
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if (wa_ctx->indirect_ctx.size == 0)
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return 0;
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vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL,
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0, CACHELINE_BYTES, 0);
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if (IS_ERR(vma))
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return PTR_ERR(vma);
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/* FIXME: we are not tracking our pinned VMA leaving it
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* up to the core to fix up the stray pin_count upon
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* free.
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*/
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wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma);
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wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1);
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memset(per_ctx_va, 0, CACHELINE_BYTES);
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update_wa_ctx_2_shadow_ctx(wa_ctx);
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return 0;
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}
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static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
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{
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/* release all the shadow batch buffer */
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if (!list_empty(&workload->shadow_bb)) {
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struct intel_shadow_bb_entry *entry_obj =
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list_first_entry(&workload->shadow_bb,
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struct intel_shadow_bb_entry,
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list);
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struct intel_shadow_bb_entry *temp;
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list_for_each_entry_safe(entry_obj, temp, &workload->shadow_bb,
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list) {
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i915_gem_object_unpin_map(entry_obj->obj);
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i915_gem_object_put(entry_obj->obj);
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list_del(&entry_obj->list);
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kfree(entry_obj);
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}
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}
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}
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static int prepare_workload(struct intel_vgpu_workload *workload)
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{
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struct intel_vgpu *vgpu = workload->vgpu;
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int ret = 0;
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if (workload->prepare)
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ret = workload->prepare(workload);
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ret = intel_vgpu_pin_mm(workload->shadow_mm);
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if (ret) {
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gvt_vgpu_err("fail to vgpu pin mm\n");
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return ret;
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}
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ret = intel_vgpu_sync_oos_pages(workload->vgpu);
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if (ret) {
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gvt_vgpu_err("fail to vgpu sync oos pages\n");
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goto err_unpin_mm;
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}
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ret = intel_vgpu_flush_post_shadow(workload->vgpu);
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if (ret) {
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gvt_vgpu_err("fail to flush post shadow\n");
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goto err_unpin_mm;
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}
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ret = prepare_shadow_batch_buffer(workload);
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if (ret) {
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gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n");
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goto err_unpin_mm;
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}
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ret = prepare_shadow_wa_ctx(&workload->wa_ctx);
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if (ret) {
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gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n");
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goto err_shadow_batch;
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}
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if (workload->prepare) {
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ret = workload->prepare(workload);
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if (ret)
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goto err_shadow_wa_ctx;
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}
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return 0;
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err_shadow_wa_ctx:
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release_shadow_wa_ctx(&workload->wa_ctx);
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err_shadow_batch:
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release_shadow_batch_buffer(workload);
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err_unpin_mm:
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intel_vgpu_unpin_mm(workload->shadow_mm);
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return ret;
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}
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@ -557,6 +701,12 @@ static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
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scheduler->current_workload[ring_id] = NULL;
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list_del_init(&workload->list);
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if (!workload->status) {
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release_shadow_batch_buffer(workload);
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release_shadow_wa_ctx(&workload->wa_ctx);
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}
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workload->complete(workload);
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atomic_dec(&s->running_workload_num);
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