forked from Minki/linux
x86/cpu/amd: Add Spectral Chicken
Zen2 uarchs have an undocumented, unnamed, MSR that contains a chicken bit for some speculation behaviour. It needs setting. Note: very belatedly AMD released naming; it's now officially called MSR_AMD64_DE_CFG2 and MSR_AMD64_DE_CFG2_SUPPRESS_NOBR_PRED_BIT but shall remain the SPECTRAL CHICKEN. Suggested-by: Andrew Cooper <Andrew.Cooper3@citrix.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Josh Poimboeuf <jpoimboe@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de>
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@ -568,6 +568,9 @@
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/* Fam 17h MSRs */
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/* Fam 17h MSRs */
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#define MSR_F17H_IRPERF 0xc00000e9
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#define MSR_F17H_IRPERF 0xc00000e9
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#define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3
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#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1)
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/* Fam 16h MSRs */
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/* Fam 16h MSRs */
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#define MSR_F16H_L2I_PERF_CTL 0xc0010230
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#define MSR_F16H_L2I_PERF_CTL 0xc0010230
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#define MSR_F16H_L2I_PERF_CTR 0xc0010231
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#define MSR_F16H_L2I_PERF_CTR 0xc0010231
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@ -862,6 +862,26 @@ static void init_amd_bd(struct cpuinfo_x86 *c)
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clear_rdrand_cpuid_bit(c);
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clear_rdrand_cpuid_bit(c);
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}
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}
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void init_spectral_chicken(struct cpuinfo_x86 *c)
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{
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u64 value;
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/*
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* On Zen2 we offer this chicken (bit) on the altar of Speculation.
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*
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* This suppresses speculation from the middle of a basic block, i.e. it
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* suppresses non-branch predictions.
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*
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* We use STIBP as a heuristic to filter out Zen2 from the rest of F17H
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*/
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if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && cpu_has(c, X86_FEATURE_AMD_STIBP)) {
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if (!rdmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) {
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value |= MSR_ZEN2_SPECTRAL_CHICKEN_BIT;
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wrmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value);
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}
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}
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}
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static void init_amd_zn(struct cpuinfo_x86 *c)
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static void init_amd_zn(struct cpuinfo_x86 *c)
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{
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{
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set_cpu_cap(c, X86_FEATURE_ZEN);
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set_cpu_cap(c, X86_FEATURE_ZEN);
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@ -907,7 +927,8 @@ static void init_amd(struct cpuinfo_x86 *c)
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case 0x12: init_amd_ln(c); break;
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case 0x12: init_amd_ln(c); break;
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case 0x15: init_amd_bd(c); break;
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case 0x15: init_amd_bd(c); break;
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case 0x16: init_amd_jg(c); break;
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case 0x16: init_amd_jg(c); break;
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case 0x17: fallthrough;
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case 0x17: init_spectral_chicken(c);
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fallthrough;
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case 0x19: init_amd_zn(c); break;
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case 0x19: init_amd_zn(c); break;
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}
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}
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@ -61,6 +61,8 @@ static inline void tsx_init(void) { }
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static inline void tsx_ap_init(void) { }
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static inline void tsx_ap_init(void) { }
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#endif /* CONFIG_CPU_SUP_INTEL */
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#endif /* CONFIG_CPU_SUP_INTEL */
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extern void init_spectral_chicken(struct cpuinfo_x86 *c);
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extern void get_cpu_cap(struct cpuinfo_x86 *c);
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extern void get_cpu_cap(struct cpuinfo_x86 *c);
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extern void get_cpu_address_sizes(struct cpuinfo_x86 *c);
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extern void get_cpu_address_sizes(struct cpuinfo_x86 *c);
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extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c);
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extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c);
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@ -302,6 +302,12 @@ static void init_hygon(struct cpuinfo_x86 *c)
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/* get apicid instead of initial apic id from cpuid */
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/* get apicid instead of initial apic id from cpuid */
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c->apicid = hard_smp_processor_id();
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c->apicid = hard_smp_processor_id();
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/*
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* XXX someone from Hygon needs to confirm this DTRT
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*
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init_spectral_chicken(c);
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*/
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set_cpu_cap(c, X86_FEATURE_ZEN);
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set_cpu_cap(c, X86_FEATURE_ZEN);
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set_cpu_cap(c, X86_FEATURE_CPB);
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set_cpu_cap(c, X86_FEATURE_CPB);
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