forked from Minki/linux
Merge tag 'arm-soc/for-4.4/soc' of http://github.com/Broadcom/stblinux into next/soc
Merge "Broadcom soc changes for v4.4 (try 2)" from Florian Fainelli: This pull request contains the following Broadcom SoC platform and driver changes: - Brian Norris create a drivers/soc/brcmstb/ stub as a place holder for SoC-specific code which is coming next - Florian Fainelli adds support for configuring the BCM7xxx SoCs Bus Interface Unit with their specific write-pairing setting, which must be saved and restored during system-wide suspend/resume, and consequently updates the brcmstb machine code to initialize the BIU - Jon Mason adds support for the Northstar Plus SoCs by introducing a custom machine descriptor matching their compatible string and setting up the PL310 L2 cache and enabling the relevant ARM errata for their Cortex-A9 * tag 'arm-soc/for-4.4/soc' of http://github.com/Broadcom/stblinux: ARM: brcmstb: Setup BIU control registers during boot soc: brcmstb: Add Bus Interface Unit control setup soc: add stubs for brcmstb SoC's ARM: NSP: Add basic support for Broadcom Northstar Plus SoC
This commit is contained in:
commit
d72b712824
@ -35,6 +35,20 @@ config ARCH_BCM_CYGNUS
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BCM11300, BCM11320, BCM11350, BCM11360,
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BCM58300, BCM58302, BCM58303, BCM58305.
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config ARCH_BCM_NSP
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bool "Broadcom Northstar Plus SoC Support" if ARCH_MULTI_V7
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select ARCH_BCM_IPROC
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select ARM_ERRATA_754322
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select ARM_ERRATA_775420
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help
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Support for Broadcom Northstar Plus SoC.
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Broadcom Northstar Plus family of SoCs are used for switching control
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and management applications as well as residential router/gateway
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applications. The SoC features dual core Cortex A9 ARM CPUs,
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integrating several peripheral interfaces including multiple Gigabit
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Ethernet PHYs, DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and
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NAND flash, SATA and several other IO controllers.
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config ARCH_BCM_5301X
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bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
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select ARCH_BCM_IPROC
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@ -147,6 +161,7 @@ config ARCH_BRCMSTB
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select BCM7120_L2_IRQ
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select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
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select ARCH_WANT_OPTIONAL_GPIOLIB
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select SOC_BRCMSTB
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help
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Say Y if you intend to run the kernel on a Broadcom ARM-based STB
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chipset.
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@ -1,5 +1,5 @@
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#
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# Copyright (C) 2012-2014 Broadcom Corporation
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# Copyright (C) 2012-2015 Broadcom Corporation
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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@ -13,6 +13,9 @@
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# Cygnus
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obj-$(CONFIG_ARCH_BCM_CYGNUS) += bcm_cygnus.o
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# Northstar Plus
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obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o
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# BCM281XX
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obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o
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25
arch/arm/mach-bcm/bcm_nsp.c
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25
arch/arm/mach-bcm/bcm_nsp.c
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@ -0,0 +1,25 @@
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/*
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* Copyright (C) 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <asm/mach/arch.h>
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static const char *const bcm_nsp_dt_compat[] __initconst = {
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"brcm,nsp",
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NULL,
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};
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DT_MACHINE_START(NSP_DT, "Broadcom Northstar Plus SoC")
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.l2c_aux_val = 0,
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.l2c_aux_mask = ~0,
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.dt_compat = bcm_nsp_dt_compat,
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MACHINE_END
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@ -12,11 +12,19 @@
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*/
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#include <linux/init.h>
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#include <linux/irqchip.h>
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#include <linux/of_platform.h>
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#include <linux/soc/brcmstb/brcmstb.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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static void __init brcmstb_init_irq(void)
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{
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irqchip_init();
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brcmstb_biuctrl_init();
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}
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static const char *const brcmstb_match[] __initconst = {
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"brcm,bcm7445",
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"brcm,brcmstb",
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@ -25,4 +33,5 @@ static const char *const brcmstb_match[] __initconst = {
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DT_MACHINE_START(BRCMSTB, "Broadcom STB (Flattened Device Tree)")
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.dt_compat = brcmstb_match,
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.init_irq = brcmstb_init_irq,
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MACHINE_END
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@ -1,5 +1,6 @@
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menu "SOC (System On Chip) specific Drivers"
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source "drivers/soc/brcmstb/Kconfig"
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source "drivers/soc/mediatek/Kconfig"
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source "drivers/soc/qcom/Kconfig"
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source "drivers/soc/sunxi/Kconfig"
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@ -2,6 +2,7 @@
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# Makefile for the Linux Kernel SOC specific device drivers.
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#
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obj-$(CONFIG_SOC_BRCMSTB) += brcmstb/
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obj-$(CONFIG_MACH_DOVE) += dove/
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obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
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obj-$(CONFIG_ARCH_QCOM) += qcom/
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9
drivers/soc/brcmstb/Kconfig
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9
drivers/soc/brcmstb/Kconfig
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@ -0,0 +1,9 @@
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menuconfig SOC_BRCMSTB
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bool "Broadcom STB SoC drivers"
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depends on ARM
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help
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Enables drivers for the Broadcom Set-Top Box (STB) series of chips.
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This option alone enables only some support code, while the drivers
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can be enabled individually within this menu.
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If unsure, say N.
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1
drivers/soc/brcmstb/Makefile
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1
drivers/soc/brcmstb/Makefile
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@ -0,0 +1 @@
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obj-y += common.o biuctrl.o
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116
drivers/soc/brcmstb/biuctrl.c
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116
drivers/soc/brcmstb/biuctrl.c
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@ -0,0 +1,116 @@
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/*
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* Broadcom STB SoCs Bus Unit Interface controls
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*
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* Copyright (C) 2015, Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "brcmstb: " KBUILD_MODNAME ": " fmt
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/syscore_ops.h>
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#define CPU_CREDIT_REG_OFFSET 0x184
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#define CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK 0x70000000
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static void __iomem *cpubiuctrl_base;
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static bool mcp_wr_pairing_en;
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static int __init mcp_write_pairing_set(void)
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{
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u32 creds = 0;
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if (!cpubiuctrl_base)
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return -1;
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creds = readl_relaxed(cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
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if (mcp_wr_pairing_en) {
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pr_info("MCP: Enabling write pairing\n");
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writel_relaxed(creds | CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
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cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
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} else if (creds & CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK) {
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pr_info("MCP: Disabling write pairing\n");
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writel_relaxed(creds & ~CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
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cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
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} else {
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pr_info("MCP: Write pairing already disabled\n");
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}
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return 0;
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}
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static int __init setup_hifcpubiuctrl_regs(void)
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{
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struct device_node *np;
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int ret = 0;
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np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
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if (!np) {
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pr_err("missing BIU control node\n");
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return -ENODEV;
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}
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cpubiuctrl_base = of_iomap(np, 0);
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if (!cpubiuctrl_base) {
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pr_err("failed to remap BIU control base\n");
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ret = -ENOMEM;
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goto out;
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}
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mcp_wr_pairing_en = of_property_read_bool(np, "brcm,write-pairing");
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out:
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of_node_put(np);
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return ret;
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}
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#ifdef CONFIG_PM_SLEEP
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static u32 cpu_credit_reg_dump; /* for save/restore */
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static int brcmstb_cpu_credit_reg_suspend(void)
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{
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if (cpubiuctrl_base)
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cpu_credit_reg_dump =
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readl_relaxed(cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
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return 0;
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}
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static void brcmstb_cpu_credit_reg_resume(void)
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{
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if (cpubiuctrl_base)
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writel_relaxed(cpu_credit_reg_dump,
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cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
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}
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static struct syscore_ops brcmstb_cpu_credit_syscore_ops = {
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.suspend = brcmstb_cpu_credit_reg_suspend,
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.resume = brcmstb_cpu_credit_reg_resume,
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};
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#endif
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void __init brcmstb_biuctrl_init(void)
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{
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int ret;
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setup_hifcpubiuctrl_regs();
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ret = mcp_write_pairing_set();
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if (ret) {
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pr_err("MCP: Unable to disable write pairing!\n");
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return;
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}
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#ifdef CONFIG_PM_SLEEP
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register_syscore_ops(&brcmstb_cpu_credit_syscore_ops);
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#endif
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}
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drivers/soc/brcmstb/common.c
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33
drivers/soc/brcmstb/common.c
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@ -0,0 +1,33 @@
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/*
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* Copyright © 2014 NVIDIA Corporation
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* Copyright © 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/of.h>
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#include <soc/brcmstb/common.h>
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static const struct of_device_id brcmstb_machine_match[] = {
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{ .compatible = "brcm,brcmstb", },
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{ }
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};
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bool soc_is_brcmstb(void)
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{
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struct device_node *root;
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root = of_find_node_by_path("/");
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if (!root)
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return false;
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return of_match_node(brcmstb_machine_match, root) != NULL;
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}
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10
include/linux/soc/brcmstb/brcmstb.h
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10
include/linux/soc/brcmstb/brcmstb.h
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@ -0,0 +1,10 @@
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#ifndef __BRCMSTB_SOC_H
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#define __BRCMSTB_SOC_H
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/*
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* Bus Interface Unit control register setup, must happen early during boot,
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* before SMP is brought up, called by machine entry point.
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*/
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void brcmstb_biuctrl_init(void);
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#endif /* __BRCMSTB_SOC_H */
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15
include/soc/brcmstb/common.h
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15
include/soc/brcmstb/common.h
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@ -0,0 +1,15 @@
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/*
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* Copyright © 2014 NVIDIA Corporation
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* Copyright © 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __SOC_BRCMSTB_COMMON_H__
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#define __SOC_BRCMSTB_COMMON_H__
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bool soc_is_brcmstb(void);
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#endif /* __SOC_BRCMSTB_COMMON_H__ */
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