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Merge branch 'topic/asoc' into for-linus

Browse Source 
Conflicts:
	sound/soc/codecs/ad1938.c
This commit is contained in:
Takashi Iwai
2010-05-20 12:00:43 +02:00
parent 19008bdacb ad8332c130
commit d71f4cece4
137 changed files with 10241 additions and 2710 deletions
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6
include/linux/i2c/twl.h
View File

@@ -569,9 +569,9 @@ struct twl4030_codec_data {
struct twl4030_codec_audio_data *audio;
struct twl4030_codec_vibra_data *vibra;
/* twl6030 */
int audpwron_gpio; /* audio power-on gpio */
int naudint_irq; /* audio interrupt */
/* twl6040 */
int audpwron_gpio; /* audio power-on gpio */
int naudint_irq; /* audio interrupt */
};
struct twl4030_platform_data {

126
include/linux/mfd/davinci_voicecodec.h Normal file
View File

@@ -0,0 +1,126 @@
/*
* DaVinci Voice Codec Core Interface for TI platforms
*
* Copyright (C) 2010 Texas Instruments, Inc
*
* Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __LINUX_MFD_DAVINCI_VOICECODEC_H_
#define __LINUX_MFD_DAVINIC_VOICECODEC_H_
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <mach/edma.h>
/*
* Register values.
*/
#define DAVINCI_VC_PID 0x00
#define DAVINCI_VC_CTRL 0x04
#define DAVINCI_VC_INTEN 0x08
#define DAVINCI_VC_INTSTATUS 0x0c
#define DAVINCI_VC_INTCLR 0x10
#define DAVINCI_VC_EMUL_CTRL 0x14
#define DAVINCI_VC_RFIFO 0x20
#define DAVINCI_VC_WFIFO 0x24
#define DAVINCI_VC_FIFOSTAT 0x28
#define DAVINCI_VC_TST_CTRL 0x2C
#define DAVINCI_VC_REG05 0x94
#define DAVINCI_VC_REG09 0xA4
#define DAVINCI_VC_REG12 0xB0
/* DAVINCI_VC_CTRL bit fields */
#define DAVINCI_VC_CTRL_MASK 0x5500
#define DAVINCI_VC_CTRL_RSTADC BIT(0)
#define DAVINCI_VC_CTRL_RSTDAC BIT(1)
#define DAVINCI_VC_CTRL_RD_BITS_8 BIT(4)
#define DAVINCI_VC_CTRL_RD_UNSIGNED BIT(5)
#define DAVINCI_VC_CTRL_WD_BITS_8 BIT(6)
#define DAVINCI_VC_CTRL_WD_UNSIGNED BIT(7)
#define DAVINCI_VC_CTRL_RFIFOEN BIT(8)
#define DAVINCI_VC_CTRL_RFIFOCL BIT(9)
#define DAVINCI_VC_CTRL_RFIFOMD_WORD_1 BIT(10)
#define DAVINCI_VC_CTRL_WFIFOEN BIT(12)
#define DAVINCI_VC_CTRL_WFIFOCL BIT(13)
#define DAVINCI_VC_CTRL_WFIFOMD_WORD_1 BIT(14)
/* DAVINCI_VC_INT bit fields */
#define DAVINCI_VC_INT_MASK 0x3F
#define DAVINCI_VC_INT_RDRDY_MASK BIT(0)
#define DAVINCI_VC_INT_RERROVF_MASK BIT(1)
#define DAVINCI_VC_INT_RERRUDR_MASK BIT(2)
#define DAVINCI_VC_INT_WDREQ_MASK BIT(3)
#define DAVINCI_VC_INT_WERROVF_MASKBIT BIT(4)
#define DAVINCI_VC_INT_WERRUDR_MASK BIT(5)
/* DAVINCI_VC_REG05 bit fields */
#define DAVINCI_VC_REG05_PGA_GAIN 0x07
/* DAVINCI_VC_REG09 bit fields */
#define DAVINCI_VC_REG09_MUTE 0x40
#define DAVINCI_VC_REG09_DIG_ATTEN 0x3F
/* DAVINCI_VC_REG12 bit fields */
#define DAVINCI_VC_REG12_POWER_ALL_ON 0xFD
#define DAVINCI_VC_REG12_POWER_ALL_OFF 0x00
#define DAVINCI_VC_CELLS 2
enum davinci_vc_cells {
DAVINCI_VC_VCIF_CELL,
DAVINCI_VC_CQ93VC_CELL,
};
struct davinci_vcif {
struct platform_device *pdev;
u32 dma_tx_channel;
u32 dma_rx_channel;
dma_addr_t dma_tx_addr;
dma_addr_t dma_rx_addr;
};
struct cq93vc {
struct platform_device *pdev;
struct snd_soc_codec *codec;
u32 sysclk;
};
struct davinci_vc;
struct davinci_vc {
/* Device data */
struct device *dev;
struct platform_device *pdev;
struct clk *clk;
/* Memory resources */
void __iomem *base;
resource_size_t pbase;
size_t base_size;
/* MFD cells */
struct mfd_cell cells[DAVINCI_VC_CELLS];
/* Client devices */
struct davinci_vcif davinci_vcif;
struct cq93vc cq93vc;
};
#endif

2
include/linux/mfd/wm8350/audio.h
View File

@@ -492,6 +492,8 @@
*/
#define WM8350_JACK_L_LVL 0x0800
#define WM8350_JACK_R_LVL 0x0400
#define WM8350_JACK_MICSCD_LVL 0x0200
#define WM8350_JACK_MICSD_LVL 0x0100
/*
* WM8350 Platform setup

53
include/linux/mfd/wm8994/core.h
View File

@@ -15,14 +15,38 @@
#ifndef __MFD_WM8994_CORE_H__
#define __MFD_WM8994_CORE_H__
#include <linux/interrupt.h>
struct regulator_dev;
struct regulator_bulk_data;
#define WM8994_NUM_GPIO_REGS 11
#define WM8994_NUM_LDO_REGS 2
#define WM8994_NUM_LDO_REGS 2
#define WM8994_NUM_IRQ_REGS 2
#define WM8994_IRQ_TEMP_SHUT 0
#define WM8994_IRQ_MIC1_DET 1
#define WM8994_IRQ_MIC1_SHRT 2
#define WM8994_IRQ_MIC2_DET 3
#define WM8994_IRQ_MIC2_SHRT 4
#define WM8994_IRQ_FLL1_LOCK 5
#define WM8994_IRQ_FLL2_LOCK 6
#define WM8994_IRQ_SRC1_LOCK 7
#define WM8994_IRQ_SRC2_LOCK 8
#define WM8994_IRQ_AIF1DRC1_SIG_DET 9
#define WM8994_IRQ_AIF1DRC2_SIG_DET 10
#define WM8994_IRQ_AIF2DRC_SIG_DET 11
#define WM8994_IRQ_FIFOS_ERR 12
#define WM8994_IRQ_WSEQ_DONE 13
#define WM8994_IRQ_DCS_DONE 14
#define WM8994_IRQ_TEMP_WARN 15
/* GPIOs in the chip are numbered from 1-11 */
#define WM8994_IRQ_GPIO(x) (x + WM8994_IRQ_TEMP_WARN)
struct wm8994 {
struct mutex io_lock;
struct mutex irq_lock;
struct device *dev;
int (*read_dev)(struct wm8994 *wm8994, unsigned short reg,
@@ -33,6 +57,11 @@ struct wm8994 {
void *control_data;
int gpio_base;
int irq_base;
int irq;
u16 irq_masks_cur[WM8994_NUM_IRQ_REGS];
u16 irq_masks_cache[WM8994_NUM_IRQ_REGS];
/* Used over suspend/resume */
u16 ldo_regs[WM8994_NUM_LDO_REGS];
@@ -51,4 +80,26 @@ int wm8994_set_bits(struct wm8994 *wm8994, unsigned short reg,
int wm8994_bulk_read(struct wm8994 *wm8994, unsigned short reg,
int count, u16 *buf);
/* Helper to save on boilerplate */
static inline int wm8994_request_irq(struct wm8994 *wm8994, int irq,
irq_handler_t handler, const char *name,
void *data)
{
if (!wm8994->irq_base)
return -EINVAL;
return request_threaded_irq(wm8994->irq_base + irq, NULL, handler,
IRQF_TRIGGER_RISING, name,
data);
}
static inline void wm8994_free_irq(struct wm8994 *wm8994, int irq, void *data)
{
if (!wm8994->irq_base)
return;
free_irq(wm8994->irq_base + irq, data);
}
int wm8994_irq_init(struct wm8994 *wm8994);
void wm8994_irq_exit(struct wm8994 *wm8994);
#endif

1
include/linux/mfd/wm8994/pdata.h
View File

@@ -70,6 +70,7 @@ struct wm8994_pdata {
struct wm8994_ldo_pdata ldo[WM8994_NUM_LDO];
int irq_base; /** Base IRQ number for WM8994, required for IRQs */
int num_drc_cfgs;
struct wm8994_drc_cfg *drc_cfgs;

7
include/sound/soc-dai.h
View File

@@ -182,6 +182,12 @@ struct snd_soc_dai_ops {
struct snd_soc_dai *);
int (*trigger)(struct snd_pcm_substream *, int,
struct snd_soc_dai *);
/*
* For hardware based FIFO caused delay reporting.
* Optional.
*/
snd_pcm_sframes_t (*delay)(struct snd_pcm_substream *,
struct snd_soc_dai *);
};
/*
@@ -215,7 +221,6 @@ struct snd_soc_dai {
unsigned int symmetric_rates:1;
/* DAI runtime info */
struct snd_pcm_runtime *runtime;
struct snd_soc_codec *codec;
unsigned int active;
unsigned char pop_wait:1;

8
include/sound/soc-dapm.h
View File

@@ -339,6 +339,9 @@ int snd_soc_dapm_disable_pin(struct snd_soc_codec *codec, const char *pin);
int snd_soc_dapm_nc_pin(struct snd_soc_codec *codec, const char *pin);
int snd_soc_dapm_get_pin_status(struct snd_soc_codec *codec, const char *pin);
int snd_soc_dapm_sync(struct snd_soc_codec *codec);
int snd_soc_dapm_force_enable_pin(struct snd_soc_codec *codec,
const char *pin);
int snd_soc_dapm_ignore_suspend(struct snd_soc_codec *codec, const char *pin);
/* dapm widget types */
enum snd_soc_dapm_type {
@@ -425,9 +428,8 @@ struct snd_soc_dapm_widget {
unsigned char connected:1; /* connected codec pin */
unsigned char new:1; /* cnew complete */
unsigned char ext:1; /* has external widgets */
unsigned char muted:1; /* muted for pop reduction */
unsigned char suspend:1; /* was active before suspend */
unsigned char pmdown:1; /* waiting for timeout */
unsigned char force:1; /* force state */
unsigned char ignore_suspend:1; /* kept enabled over suspend */
int (*power_check)(struct snd_soc_dapm_widget *w);

61
include/sound/soc.h
View File

@@ -15,6 +15,7 @@
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/notifier.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
@@ -29,10 +30,10 @@
#define SOC_SINGLE_VALUE(xreg, xshift, xmax, xinvert) \
((unsigned long)&(struct soc_mixer_control) \
{.reg = xreg, .shift = xshift, .rshift = xshift, .max = xmax, \
.invert = xinvert})
.platform_max = xmax, .invert = xinvert})
#define SOC_SINGLE_VALUE_EXT(xreg, xmax, xinvert) \
((unsigned long)&(struct soc_mixer_control) \
{.reg = xreg, .max = xmax, .invert = xinvert})
{.reg = xreg, .max = xmax, .platform_max = xmax, .invert = xinvert})
#define SOC_SINGLE(xname, reg, shift, max, invert) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
@@ -52,14 +53,14 @@
.put = snd_soc_put_volsw, \
.private_value = (unsigned long)&(struct soc_mixer_control) \
{.reg = xreg, .shift = shift_left, .rshift = shift_right, \
.max = xmax, .invert = xinvert} }
.max = xmax, .platform_max = xmax, .invert = xinvert} }
#define SOC_DOUBLE_R(xname, reg_left, reg_right, xshift, xmax, xinvert) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
.info = snd_soc_info_volsw_2r, \
.get = snd_soc_get_volsw_2r, .put = snd_soc_put_volsw_2r, \
.private_value = (unsigned long)&(struct soc_mixer_control) \
{.reg = reg_left, .rreg = reg_right, .shift = xshift, \
.max = xmax, .invert = xinvert} }
.max = xmax, .platform_max = xmax, .invert = xinvert} }
#define SOC_DOUBLE_TLV(xname, xreg, shift_left, shift_right, xmax, xinvert, tlv_array) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
@@ -69,7 +70,7 @@
.put = snd_soc_put_volsw, \
.private_value = (unsigned long)&(struct soc_mixer_control) \
{.reg = xreg, .shift = shift_left, .rshift = shift_right,\
.max = xmax, .invert = xinvert} }
.max = xmax, .platform_max = xmax, .invert = xinvert} }
#define SOC_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, xinvert, tlv_array) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
@@ -79,7 +80,7 @@
.get = snd_soc_get_volsw_2r, .put = snd_soc_put_volsw_2r, \
.private_value = (unsigned long)&(struct soc_mixer_control) \
{.reg = reg_left, .rreg = reg_right, .shift = xshift, \
.max = xmax, .invert = xinvert} }
.max = xmax, .platform_max = xmax, .invert = xinvert} }
#define SOC_DOUBLE_S8_TLV(xname, xreg, xmin, xmax, tlv_array) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
@@ -88,7 +89,8 @@
.info = snd_soc_info_volsw_s8, .get = snd_soc_get_volsw_s8, \
.put = snd_soc_put_volsw_s8, \
.private_value = (unsigned long)&(struct soc_mixer_control) \
{.reg = xreg, .min = xmin, .max = xmax} }
{.reg = xreg, .min = xmin, .max = xmax, \
.platform_max = xmax} }
#define SOC_ENUM_DOUBLE(xreg, xshift_l, xshift_r, xmax, xtexts) \
{ .reg = xreg, .shift_l = xshift_l, .shift_r = xshift_r, \
.max = xmax, .texts = xtexts }
@@ -125,7 +127,7 @@
.get = xhandler_get, .put = xhandler_put, \
.private_value = (unsigned long)&(struct soc_mixer_control) \
{.reg = xreg, .shift = shift_left, .rshift = shift_right, \
.max = xmax, .invert = xinvert} }
.max = xmax, .platform_max = xmax, .invert = xinvert} }
#define SOC_SINGLE_EXT_TLV(xname, xreg, xshift, xmax, xinvert,\
xhandler_get, xhandler_put, tlv_array) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
@@ -145,7 +147,7 @@
.get = xhandler_get, .put = xhandler_put, \
.private_value = (unsigned long)&(struct soc_mixer_control) \
{.reg = xreg, .shift = shift_left, .rshift = shift_right, \
.max = xmax, .invert = xinvert} }
.max = xmax, .platform_max = xmax, .invert = xinvert} }
#define SOC_DOUBLE_R_EXT_TLV(xname, reg_left, reg_right, xshift, xmax, xinvert,\
xhandler_get, xhandler_put, tlv_array) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
@@ -156,7 +158,7 @@
.get = xhandler_get, .put = xhandler_put, \
.private_value = (unsigned long)&(struct soc_mixer_control) \
{.reg = reg_left, .rreg = reg_right, .shift = xshift, \
.max = xmax, .invert = xinvert} }
.max = xmax, .platform_max = xmax, .invert = xinvert} }
#define SOC_SINGLE_BOOL_EXT(xname, xdata, xhandler_get, xhandler_put) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = snd_soc_info_bool_ext, \
@@ -212,6 +214,7 @@ struct snd_soc_dai_mode;
struct snd_soc_pcm_runtime;
struct snd_soc_dai;
struct snd_soc_platform;
struct snd_soc_dai_link;
struct snd_soc_codec;
struct soc_enum;
struct snd_soc_ac97_ops;
@@ -260,6 +263,10 @@ int snd_soc_jack_new(struct snd_soc_card *card, const char *id, int type,
void snd_soc_jack_report(struct snd_soc_jack *jack, int status, int mask);
int snd_soc_jack_add_pins(struct snd_soc_jack *jack, int count,
struct snd_soc_jack_pin *pins);
void snd_soc_jack_notifier_register(struct snd_soc_jack *jack,
struct notifier_block *nb);
void snd_soc_jack_notifier_unregister(struct snd_soc_jack *jack,
struct notifier_block *nb);
#ifdef CONFIG_GPIOLIB
int snd_soc_jack_add_gpios(struct snd_soc_jack *jack, int count,
struct snd_soc_jack_gpio *gpios);
@@ -320,6 +327,8 @@ int snd_soc_get_volsw_s8(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int snd_soc_put_volsw_s8(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int snd_soc_limit_volume(struct snd_soc_codec *codec,
const char *name, int max);
/**
* struct snd_soc_jack_pin - Describes a pin to update based on jack detection
@@ -363,6 +372,7 @@ struct snd_soc_jack {
struct snd_soc_card *card;
struct list_head pins;
int status;
struct blocking_notifier_head notifier;
};
/* SoC PCM stream information */
@@ -374,7 +384,7 @@ struct snd_soc_pcm_stream {
unsigned int rate_max; /* max rate */
unsigned int channels_min; /* min channels */
unsigned int channels_max; /* max channels */
unsigned int active:1; /* stream is in use */
unsigned int active; /* stream is in use */
void *dma_data; /* used by platform code */
};
@@ -407,7 +417,7 @@ struct snd_soc_codec {
struct snd_ac97 *ac97; /* for ad-hoc ac97 devices */
unsigned int active;
unsigned int pcm_devs;
void *private_data;
void *drvdata;
/* codec IO */
void *control_data; /* codec control (i2c/3wire) data */
@@ -462,14 +472,21 @@ struct snd_soc_platform {
int (*probe)(struct platform_device *pdev);
int (*remove)(struct platform_device *pdev);
int (*suspend)(struct snd_soc_dai *dai);
int (*resume)(struct snd_soc_dai *dai);
int (*suspend)(struct snd_soc_dai_link *dai_link);
int (*resume)(struct snd_soc_dai_link *dai_link);
/* pcm creation and destruction */
int (*pcm_new)(struct snd_card *, struct snd_soc_dai *,
struct snd_pcm *);
void (*pcm_free)(struct snd_pcm *);
/*
* For platform caused delay reporting.
* Optional.
*/
snd_pcm_sframes_t (*delay)(struct snd_pcm_substream *,
struct snd_soc_dai *);
/* platform stream ops */
struct snd_pcm_ops *pcm_ops;
};
@@ -489,6 +506,9 @@ struct snd_soc_dai_link {
/* codec/machine specific init - e.g. add machine controls */
int (*init)(struct snd_soc_codec *codec);
/* Keep DAI active over suspend */
unsigned int ignore_suspend:1;
/* Symmetry requirements */
unsigned int symmetric_rates:1;
@@ -553,7 +573,7 @@ struct snd_soc_pcm_runtime {
/* mixer control */
struct soc_mixer_control {
int min, max;
int min, max, platform_max;
unsigned int reg, rreg, shift, rshift, invert;
};
@@ -583,6 +603,17 @@ static inline unsigned int snd_soc_write(struct snd_soc_codec *codec,
return codec->write(codec, reg, val);
}
static inline void snd_soc_codec_set_drvdata(struct snd_soc_codec *codec,
void *data)
{
codec->drvdata = data;
}
static inline void *snd_soc_codec_get_drvdata(struct snd_soc_codec *codec)
{
return codec->drvdata;
}
#include <sound/soc-dai.h>
#endif

17
include/sound/tlv320aic3x.h Normal file
View File

@@ -0,0 +1,17 @@
/*
* Platform data for Texas Instruments TLV320AIC3x codec
*
* Author: Jarkko Nikula <jhnikula@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __TLV320AIC3x_H__
#define __TLV320AIC3x_H__
struct aic3x_pdata {
int gpio_reset; /* < 0 if not used */
};
#endif

1
include/sound/tlv320dac33-plat.h
View File

@@ -15,6 +15,7 @@
struct tlv320dac33_platform_data {
int power_gpio;
int keep_bclk; /* Keep the BCLK running in FIFO modes */
u8 burst_bclkdiv;
};

1
include/sound/uda134x.h
View File

@@ -21,6 +21,7 @@ struct uda134x_platform_data {
#define UDA134X_UDA1340 1
#define UDA134X_UDA1341 2
#define UDA134X_UDA1344 3
#define UDA134X_UDA1345 4
};
#endif /* _UDA134X_H */

249
include/sound/wm8903.h Normal file
View File

@@ -0,0 +1,249 @@
/*
* linux/sound/wm8903.h -- Platform data for WM8903
*
* Copyright 2010 Wolfson Microelectronics. PLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_SND_WM8903_H
#define __LINUX_SND_WM8903_H
/* Used to enable configuration of a GPIO to all zeros */
#define WM8903_GPIO_NO_CONFIG 0x8000
/*
* R6 (0x06) - Mic Bias Control 0
*/
#define WM8903_MICDET_HYST_ENA 0x0080 /* MICDET_HYST_ENA */
#define WM8903_MICDET_HYST_ENA_MASK 0x0080 /* MICDET_HYST_ENA */
#define WM8903_MICDET_HYST_ENA_SHIFT 7 /* MICDET_HYST_ENA */
#define WM8903_MICDET_HYST_ENA_WIDTH 1 /* MICDET_HYST_ENA */
#define WM8903_MICDET_THR_MASK 0x0070 /* MICDET_THR - [6:4] */
#define WM8903_MICDET_THR_SHIFT 4 /* MICDET_THR - [6:4] */
#define WM8903_MICDET_THR_WIDTH 3 /* MICDET_THR - [6:4] */
#define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */
#define WM8903_MICSHORT_THR_SHIFT 2 /* MICSHORT_THR - [3:2] */
#define WM8903_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [3:2] */
#define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */
#define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */
#define WM8903_MICDET_ENA_SHIFT 1 /* MICDET_ENA */
#define WM8903_MICDET_ENA_WIDTH 1 /* MICDET_ENA */
#define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */
#define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */
#define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */
#define WM8903_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */
/*
* R116 (0x74) - GPIO Control 1
*/
#define WM8903_GP1_FN_MASK 0x1F00 /* GP1_FN - [12:8] */
#define WM8903_GP1_FN_SHIFT 8 /* GP1_FN - [12:8] */
#define WM8903_GP1_FN_WIDTH 5 /* GP1_FN - [12:8] */
#define WM8903_GP1_DIR 0x0080 /* GP1_DIR */
#define WM8903_GP1_DIR_MASK 0x0080 /* GP1_DIR */
#define WM8903_GP1_DIR_SHIFT 7 /* GP1_DIR */
#define WM8903_GP1_DIR_WIDTH 1 /* GP1_DIR */
#define WM8903_GP1_OP_CFG 0x0040 /* GP1_OP_CFG */
#define WM8903_GP1_OP_CFG_MASK 0x0040 /* GP1_OP_CFG */
#define WM8903_GP1_OP_CFG_SHIFT 6 /* GP1_OP_CFG */
#define WM8903_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */
#define WM8903_GP1_IP_CFG 0x0020 /* GP1_IP_CFG */
#define WM8903_GP1_IP_CFG_MASK 0x0020 /* GP1_IP_CFG */
#define WM8903_GP1_IP_CFG_SHIFT 5 /* GP1_IP_CFG */
#define WM8903_GP1_IP_CFG_WIDTH 1 /* GP1_IP_CFG */
#define WM8903_GP1_LVL 0x0010 /* GP1_LVL */
#define WM8903_GP1_LVL_MASK 0x0010 /* GP1_LVL */
#define WM8903_GP1_LVL_SHIFT 4 /* GP1_LVL */
#define WM8903_GP1_LVL_WIDTH 1 /* GP1_LVL */
#define WM8903_GP1_PD 0x0008 /* GP1_PD */
#define WM8903_GP1_PD_MASK 0x0008 /* GP1_PD */
#define WM8903_GP1_PD_SHIFT 3 /* GP1_PD */
#define WM8903_GP1_PD_WIDTH 1 /* GP1_PD */
#define WM8903_GP1_PU 0x0004 /* GP1_PU */
#define WM8903_GP1_PU_MASK 0x0004 /* GP1_PU */
#define WM8903_GP1_PU_SHIFT 2 /* GP1_PU */
#define WM8903_GP1_PU_WIDTH 1 /* GP1_PU */
#define WM8903_GP1_INTMODE 0x0002 /* GP1_INTMODE */
#define WM8903_GP1_INTMODE_MASK 0x0002 /* GP1_INTMODE */
#define WM8903_GP1_INTMODE_SHIFT 1 /* GP1_INTMODE */
#define WM8903_GP1_INTMODE_WIDTH 1 /* GP1_INTMODE */
#define WM8903_GP1_DB 0x0001 /* GP1_DB */
#define WM8903_GP1_DB_MASK 0x0001 /* GP1_DB */
#define WM8903_GP1_DB_SHIFT 0 /* GP1_DB */
#define WM8903_GP1_DB_WIDTH 1 /* GP1_DB */
/*
* R117 (0x75) - GPIO Control 2
*/
#define WM8903_GP2_FN_MASK 0x1F00 /* GP2_FN - [12:8] */
#define WM8903_GP2_FN_SHIFT 8 /* GP2_FN - [12:8] */
#define WM8903_GP2_FN_WIDTH 5 /* GP2_FN - [12:8] */
#define WM8903_GP2_DIR 0x0080 /* GP2_DIR */
#define WM8903_GP2_DIR_MASK 0x0080 /* GP2_DIR */
#define WM8903_GP2_DIR_SHIFT 7 /* GP2_DIR */
#define WM8903_GP2_DIR_WIDTH 1 /* GP2_DIR */
#define WM8903_GP2_OP_CFG 0x0040 /* GP2_OP_CFG */
#define WM8903_GP2_OP_CFG_MASK 0x0040 /* GP2_OP_CFG */
#define WM8903_GP2_OP_CFG_SHIFT 6 /* GP2_OP_CFG */
#define WM8903_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */
#define WM8903_GP2_IP_CFG 0x0020 /* GP2_IP_CFG */
#define WM8903_GP2_IP_CFG_MASK 0x0020 /* GP2_IP_CFG */
#define WM8903_GP2_IP_CFG_SHIFT 5 /* GP2_IP_CFG */
#define WM8903_GP2_IP_CFG_WIDTH 1 /* GP2_IP_CFG */
#define WM8903_GP2_LVL 0x0010 /* GP2_LVL */
#define WM8903_GP2_LVL_MASK 0x0010 /* GP2_LVL */
#define WM8903_GP2_LVL_SHIFT 4 /* GP2_LVL */
#define WM8903_GP2_LVL_WIDTH 1 /* GP2_LVL */
#define WM8903_GP2_PD 0x0008 /* GP2_PD */
#define WM8903_GP2_PD_MASK 0x0008 /* GP2_PD */
#define WM8903_GP2_PD_SHIFT 3 /* GP2_PD */
#define WM8903_GP2_PD_WIDTH 1 /* GP2_PD */
#define WM8903_GP2_PU 0x0004 /* GP2_PU */
#define WM8903_GP2_PU_MASK 0x0004 /* GP2_PU */
#define WM8903_GP2_PU_SHIFT 2 /* GP2_PU */
#define WM8903_GP2_PU_WIDTH 1 /* GP2_PU */
#define WM8903_GP2_INTMODE 0x0002 /* GP2_INTMODE */
#define WM8903_GP2_INTMODE_MASK 0x0002 /* GP2_INTMODE */
#define WM8903_GP2_INTMODE_SHIFT 1 /* GP2_INTMODE */
#define WM8903_GP2_INTMODE_WIDTH 1 /* GP2_INTMODE */
#define WM8903_GP2_DB 0x0001 /* GP2_DB */
#define WM8903_GP2_DB_MASK 0x0001 /* GP2_DB */
#define WM8903_GP2_DB_SHIFT 0 /* GP2_DB */
#define WM8903_GP2_DB_WIDTH 1 /* GP2_DB */
/*
* R118 (0x76) - GPIO Control 3
*/
#define WM8903_GP3_FN_MASK 0x1F00 /* GP3_FN - [12:8] */
#define WM8903_GP3_FN_SHIFT 8 /* GP3_FN - [12:8] */
#define WM8903_GP3_FN_WIDTH 5 /* GP3_FN - [12:8] */
#define WM8903_GP3_DIR 0x0080 /* GP3_DIR */
#define WM8903_GP3_DIR_MASK 0x0080 /* GP3_DIR */
#define WM8903_GP3_DIR_SHIFT 7 /* GP3_DIR */
#define WM8903_GP3_DIR_WIDTH 1 /* GP3_DIR */
#define WM8903_GP3_OP_CFG 0x0040 /* GP3_OP_CFG */
#define WM8903_GP3_OP_CFG_MASK 0x0040 /* GP3_OP_CFG */
#define WM8903_GP3_OP_CFG_SHIFT 6 /* GP3_OP_CFG */
#define WM8903_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */
#define WM8903_GP3_IP_CFG 0x0020 /* GP3_IP_CFG */
#define WM8903_GP3_IP_CFG_MASK 0x0020 /* GP3_IP_CFG */
#define WM8903_GP3_IP_CFG_SHIFT 5 /* GP3_IP_CFG */
#define WM8903_GP3_IP_CFG_WIDTH 1 /* GP3_IP_CFG */
#define WM8903_GP3_LVL 0x0010 /* GP3_LVL */
#define WM8903_GP3_LVL_MASK 0x0010 /* GP3_LVL */
#define WM8903_GP3_LVL_SHIFT 4 /* GP3_LVL */
#define WM8903_GP3_LVL_WIDTH 1 /* GP3_LVL */
#define WM8903_GP3_PD 0x0008 /* GP3_PD */
#define WM8903_GP3_PD_MASK 0x0008 /* GP3_PD */
#define WM8903_GP3_PD_SHIFT 3 /* GP3_PD */
#define WM8903_GP3_PD_WIDTH 1 /* GP3_PD */
#define WM8903_GP3_PU 0x0004 /* GP3_PU */
#define WM8903_GP3_PU_MASK 0x0004 /* GP3_PU */
#define WM8903_GP3_PU_SHIFT 2 /* GP3_PU */
#define WM8903_GP3_PU_WIDTH 1 /* GP3_PU */
#define WM8903_GP3_INTMODE 0x0002 /* GP3_INTMODE */
#define WM8903_GP3_INTMODE_MASK 0x0002 /* GP3_INTMODE */
#define WM8903_GP3_INTMODE_SHIFT 1 /* GP3_INTMODE */
#define WM8903_GP3_INTMODE_WIDTH 1 /* GP3_INTMODE */
#define WM8903_GP3_DB 0x0001 /* GP3_DB */
#define WM8903_GP3_DB_MASK 0x0001 /* GP3_DB */
#define WM8903_GP3_DB_SHIFT 0 /* GP3_DB */
#define WM8903_GP3_DB_WIDTH 1 /* GP3_DB */
/*
* R119 (0x77) - GPIO Control 4
*/
#define WM8903_GP4_FN_MASK 0x1F00 /* GP4_FN - [12:8] */
#define WM8903_GP4_FN_SHIFT 8 /* GP4_FN - [12:8] */
#define WM8903_GP4_FN_WIDTH 5 /* GP4_FN - [12:8] */
#define WM8903_GP4_DIR 0x0080 /* GP4_DIR */
#define WM8903_GP4_DIR_MASK 0x0080 /* GP4_DIR */
#define WM8903_GP4_DIR_SHIFT 7 /* GP4_DIR */
#define WM8903_GP4_DIR_WIDTH 1 /* GP4_DIR */
#define WM8903_GP4_OP_CFG 0x0040 /* GP4_OP_CFG */
#define WM8903_GP4_OP_CFG_MASK 0x0040 /* GP4_OP_CFG */
#define WM8903_GP4_OP_CFG_SHIFT 6 /* GP4_OP_CFG */
#define WM8903_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */
#define WM8903_GP4_IP_CFG 0x0020 /* GP4_IP_CFG */
#define WM8903_GP4_IP_CFG_MASK 0x0020 /* GP4_IP_CFG */
#define WM8903_GP4_IP_CFG_SHIFT 5 /* GP4_IP_CFG */
#define WM8903_GP4_IP_CFG_WIDTH 1 /* GP4_IP_CFG */
#define WM8903_GP4_LVL 0x0010 /* GP4_LVL */
#define WM8903_GP4_LVL_MASK 0x0010 /* GP4_LVL */
#define WM8903_GP4_LVL_SHIFT 4 /* GP4_LVL */
#define WM8903_GP4_LVL_WIDTH 1 /* GP4_LVL */
#define WM8903_GP4_PD 0x0008 /* GP4_PD */
#define WM8903_GP4_PD_MASK 0x0008 /* GP4_PD */
#define WM8903_GP4_PD_SHIFT 3 /* GP4_PD */
#define WM8903_GP4_PD_WIDTH 1 /* GP4_PD */
#define WM8903_GP4_PU 0x0004 /* GP4_PU */
#define WM8903_GP4_PU_MASK 0x0004 /* GP4_PU */
#define WM8903_GP4_PU_SHIFT 2 /* GP4_PU */
#define WM8903_GP4_PU_WIDTH 1 /* GP4_PU */
#define WM8903_GP4_INTMODE 0x0002 /* GP4_INTMODE */
#define WM8903_GP4_INTMODE_MASK 0x0002 /* GP4_INTMODE */
#define WM8903_GP4_INTMODE_SHIFT 1 /* GP4_INTMODE */
#define WM8903_GP4_INTMODE_WIDTH 1 /* GP4_INTMODE */
#define WM8903_GP4_DB 0x0001 /* GP4_DB */
#define WM8903_GP4_DB_MASK 0x0001 /* GP4_DB */
#define WM8903_GP4_DB_SHIFT 0 /* GP4_DB */
#define WM8903_GP4_DB_WIDTH 1 /* GP4_DB */
/*
* R120 (0x78) - GPIO Control 5
*/
#define WM8903_GP5_FN_MASK 0x1F00 /* GP5_FN - [12:8] */
#define WM8903_GP5_FN_SHIFT 8 /* GP5_FN - [12:8] */
#define WM8903_GP5_FN_WIDTH 5 /* GP5_FN - [12:8] */
#define WM8903_GP5_DIR 0x0080 /* GP5_DIR */
#define WM8903_GP5_DIR_MASK 0x0080 /* GP5_DIR */
#define WM8903_GP5_DIR_SHIFT 7 /* GP5_DIR */
#define WM8903_GP5_DIR_WIDTH 1 /* GP5_DIR */
#define WM8903_GP5_OP_CFG 0x0040 /* GP5_OP_CFG */
#define WM8903_GP5_OP_CFG_MASK 0x0040 /* GP5_OP_CFG */
#define WM8903_GP5_OP_CFG_SHIFT 6 /* GP5_OP_CFG */
#define WM8903_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */
#define WM8903_GP5_IP_CFG 0x0020 /* GP5_IP_CFG */
#define WM8903_GP5_IP_CFG_MASK 0x0020 /* GP5_IP_CFG */
#define WM8903_GP5_IP_CFG_SHIFT 5 /* GP5_IP_CFG */
#define WM8903_GP5_IP_CFG_WIDTH 1 /* GP5_IP_CFG */
#define WM8903_GP5_LVL 0x0010 /* GP5_LVL */
#define WM8903_GP5_LVL_MASK 0x0010 /* GP5_LVL */
#define WM8903_GP5_LVL_SHIFT 4 /* GP5_LVL */
#define WM8903_GP5_LVL_WIDTH 1 /* GP5_LVL */
#define WM8903_GP5_PD 0x0008 /* GP5_PD */
#define WM8903_GP5_PD_MASK 0x0008 /* GP5_PD */
#define WM8903_GP5_PD_SHIFT 3 /* GP5_PD */
#define WM8903_GP5_PD_WIDTH 1 /* GP5_PD */
#define WM8903_GP5_PU 0x0004 /* GP5_PU */
#define WM8903_GP5_PU_MASK 0x0004 /* GP5_PU */
#define WM8903_GP5_PU_SHIFT 2 /* GP5_PU */
#define WM8903_GP5_PU_WIDTH 1 /* GP5_PU */
#define WM8903_GP5_INTMODE 0x0002 /* GP5_INTMODE */
#define WM8903_GP5_INTMODE_MASK 0x0002 /* GP5_INTMODE */
#define WM8903_GP5_INTMODE_SHIFT 1 /* GP5_INTMODE */
#define WM8903_GP5_INTMODE_WIDTH 1 /* GP5_INTMODE */
#define WM8903_GP5_DB 0x0001 /* GP5_DB */
#define WM8903_GP5_DB_MASK 0x0001 /* GP5_DB */
#define WM8903_GP5_DB_SHIFT 0 /* GP5_DB */
#define WM8903_GP5_DB_WIDTH 1 /* GP5_DB */
struct wm8903_platform_data {
bool irq_active_low; /* Set if IRQ active low, default high */
/* Default register value for R6 (Mic bias), used to configure
* microphone detection. In conjunction with gpio_cfg this
* can be used to route the microphone status signals out onto
* the GPIOs for use with snd_soc_jack_add_gpios().
*/
u16 micdet_cfg;
int micdet_delay; /* Delay after microphone detection (ms) */
u32 gpio_cfg[5]; /* Default register values for GPIO pin mux */
};
#endif

110
include/sound/wm8904.h
View File

@@ -15,8 +15,111 @@
#ifndef __MFD_WM8994_PDATA_H__
#define __MFD_WM8994_PDATA_H__
#define WM8904_DRC_REGS 4
#define WM8904_EQ_REGS 25
/* Used to enable configuration of a GPIO to all zeros */
#define WM8904_GPIO_NO_CONFIG 0x8000
/*
* R6 (0x06) - Mic Bias Control 0
*/
#define WM8904_MICDET_THR_MASK 0x0070 /* MICDET_THR - [6:4] */
#define WM8904_MICDET_THR_SHIFT 4 /* MICDET_THR - [6:4] */
#define WM8904_MICDET_THR_WIDTH 3 /* MICDET_THR - [6:4] */
#define WM8904_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */
#define WM8904_MICSHORT_THR_SHIFT 2 /* MICSHORT_THR - [3:2] */
#define WM8904_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [3:2] */
#define WM8904_MICDET_ENA 0x0002 /* MICDET_ENA */
#define WM8904_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */
#define WM8904_MICDET_ENA_SHIFT 1 /* MICDET_ENA */
#define WM8904_MICDET_ENA_WIDTH 1 /* MICDET_ENA */
#define WM8904_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */
#define WM8904_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */
#define WM8904_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */
#define WM8904_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */
/*
* R7 (0x07) - Mic Bias Control 1
*/
#define WM8904_MIC_DET_FILTER_ENA 0x8000 /* MIC_DET_FILTER_ENA */
#define WM8904_MIC_DET_FILTER_ENA_MASK 0x8000 /* MIC_DET_FILTER_ENA */
#define WM8904_MIC_DET_FILTER_ENA_SHIFT 15 /* MIC_DET_FILTER_ENA */
#define WM8904_MIC_DET_FILTER_ENA_WIDTH 1 /* MIC_DET_FILTER_ENA */
#define WM8904_MIC_SHORT_FILTER_ENA 0x4000 /* MIC_SHORT_FILTER_ENA */
#define WM8904_MIC_SHORT_FILTER_ENA_MASK 0x4000 /* MIC_SHORT_FILTER_ENA */
#define WM8904_MIC_SHORT_FILTER_ENA_SHIFT 14 /* MIC_SHORT_FILTER_ENA */
#define WM8904_MIC_SHORT_FILTER_ENA_WIDTH 1 /* MIC_SHORT_FILTER_ENA */
#define WM8904_MICBIAS_SEL_MASK 0x0007 /* MICBIAS_SEL - [2:0] */
#define WM8904_MICBIAS_SEL_SHIFT 0 /* MICBIAS_SEL - [2:0] */
#define WM8904_MICBIAS_SEL_WIDTH 3 /* MICBIAS_SEL - [2:0] */
/*
* R121 (0x79) - GPIO Control 1
*/
#define WM8904_GPIO1_PU 0x0020 /* GPIO1_PU */
#define WM8904_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */
#define WM8904_GPIO1_PU_SHIFT 5 /* GPIO1_PU */
#define WM8904_GPIO1_PU_WIDTH 1 /* GPIO1_PU */
#define WM8904_GPIO1_PD 0x0010 /* GPIO1_PD */
#define WM8904_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */
#define WM8904_GPIO1_PD_SHIFT 4 /* GPIO1_PD */
#define WM8904_GPIO1_PD_WIDTH 1 /* GPIO1_PD */
#define WM8904_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */
#define WM8904_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */
#define WM8904_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */
/*
* R122 (0x7A) - GPIO Control 2
*/
#define WM8904_GPIO2_PU 0x0020 /* GPIO2_PU */
#define WM8904_GPIO2_PU_MASK 0x0020 /* GPIO2_PU */
#define WM8904_GPIO2_PU_SHIFT 5 /* GPIO2_PU */
#define WM8904_GPIO2_PU_WIDTH 1 /* GPIO2_PU */
#define WM8904_GPIO2_PD 0x0010 /* GPIO2_PD */
#define WM8904_GPIO2_PD_MASK 0x0010 /* GPIO2_PD */
#define WM8904_GPIO2_PD_SHIFT 4 /* GPIO2_PD */
#define WM8904_GPIO2_PD_WIDTH 1 /* GPIO2_PD */
#define WM8904_GPIO2_SEL_MASK 0x000F /* GPIO2_SEL - [3:0] */
#define WM8904_GPIO2_SEL_SHIFT 0 /* GPIO2_SEL - [3:0] */
#define WM8904_GPIO2_SEL_WIDTH 4 /* GPIO2_SEL - [3:0] */
/*
* R123 (0x7B) - GPIO Control 3
*/
#define WM8904_GPIO3_PU 0x0020 /* GPIO3_PU */
#define WM8904_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */
#define WM8904_GPIO3_PU_SHIFT 5 /* GPIO3_PU */
#define WM8904_GPIO3_PU_WIDTH 1 /* GPIO3_PU */
#define WM8904_GPIO3_PD 0x0010 /* GPIO3_PD */
#define WM8904_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */
#define WM8904_GPIO3_PD_SHIFT 4 /* GPIO3_PD */
#define WM8904_GPIO3_PD_WIDTH 1 /* GPIO3_PD */
#define WM8904_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */
#define WM8904_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */
#define WM8904_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */
/*
* R124 (0x7C) - GPIO Control 4
*/
#define WM8904_GPI7_ENA 0x0200 /* GPI7_ENA */
#define WM8904_GPI7_ENA_MASK 0x0200 /* GPI7_ENA */
#define WM8904_GPI7_ENA_SHIFT 9 /* GPI7_ENA */
#define WM8904_GPI7_ENA_WIDTH 1 /* GPI7_ENA */
#define WM8904_GPI8_ENA 0x0100 /* GPI8_ENA */
#define WM8904_GPI8_ENA_MASK 0x0100 /* GPI8_ENA */
#define WM8904_GPI8_ENA_SHIFT 8 /* GPI8_ENA */
#define WM8904_GPI8_ENA_WIDTH 1 /* GPI8_ENA */
#define WM8904_GPIO_BCLK_MODE_ENA 0x0080 /* GPIO_BCLK_MODE_ENA */
#define WM8904_GPIO_BCLK_MODE_ENA_MASK 0x0080 /* GPIO_BCLK_MODE_ENA */
#define WM8904_GPIO_BCLK_MODE_ENA_SHIFT 7 /* GPIO_BCLK_MODE_ENA */
#define WM8904_GPIO_BCLK_MODE_ENA_WIDTH 1 /* GPIO_BCLK_MODE_ENA */
#define WM8904_GPIO_BCLK_SEL_MASK 0x000F /* GPIO_BCLK_SEL - [3:0] */
#define WM8904_GPIO_BCLK_SEL_SHIFT 0 /* GPIO_BCLK_SEL - [3:0] */
#define WM8904_GPIO_BCLK_SEL_WIDTH 4 /* GPIO_BCLK_SEL - [3:0] */
#define WM8904_MIC_REGS 2
#define WM8904_GPIO_REGS 4
#define WM8904_DRC_REGS 4
#define WM8904_EQ_REGS 25
/**
* DRC configurations are specified with a label and a set of register
@@ -52,6 +155,9 @@ struct wm8904_pdata {
int num_retune_mobile_cfgs;
struct wm8904_retune_mobile_cfg *retune_mobile_cfgs;
u32 gpio_cfg[WM8904_GPIO_REGS];
u32 mic_cfg[WM8904_MIC_REGS];
};
#endif

24
include/sound/wm8960.h Normal file
View File

@@ -0,0 +1,24 @@
/*
* wm8960.h -- WM8960 Soc Audio driver platform data
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _WM8960_PDATA_H
#define _WM8960_PDATA_H
#define WM8960_DRES_400R 0
#define WM8960_DRES_200R 1
#define WM8960_DRES_600R 2
#define WM8960_DRES_150R 3
#define WM8960_DRES_MAX 3
struct wm8960_data {
bool capless; /* Headphone outputs configured in capless mode */
int dres; /* Discharge resistance for headphone outputs */
};
#endif

28
include/sound/wm9090.h Normal file
View File

@@ -0,0 +1,28 @@
/*
* linux/sound/wm9090.h -- Platform data for WM9090
*
* Copyright 2009, 2010 Wolfson Microelectronics. PLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_SND_WM9090_H
#define __LINUX_SND_WM9090_H
struct wm9090_platform_data {
/* Line inputs 1 & 2 can optionally be differential */
unsigned int lin1_diff:1;
unsigned int lin2_diff:1;
/* AGC configuration. This is intended to protect the speaker
* against overdriving and will therefore depend on the
* hardware setup with incorrect runtime configuration
* potentially causing hardware damage.
*/
unsigned int agc_ena:1;
u16 agc[3];
};
#endif