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ARM: dts: STi: Fix bindings notation

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Remove leading 0x and 0s from bindings notation
Add missing unit-address and remove some which are useless.

This allows to fix several warnings like :

Warning (unit_address_vs_reg): Node XXXX has a reg or ranges property, but no unit name
Warning (simple_bus_reg): Node XXXX simple-bus unit address format error, expected "123456"
Warning (unit_address_vs_reg): Node XXXX has a unit name, but no reg property

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Patrice Chotard 2018-01-08 11:20:42 +01:00
parent 7928b2cbe5
commit d6d854cc1c
12 changed files with 25 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/stih407-b2120.dts
View File

@ -18,7 +18,7 @@
linux,stdout-path = &sbc_serial0; linux,stdout-path = &sbc_serial0;
}; };
memory { memory@40000000 {
device_type = "memory"; device_type = "memory";
reg = <0x40000000 0x80000000>; reg = <0x40000000 0x80000000>;
}; };

4
arch/arm/boot/dts/stih407-clock.dtsi
View File

@ -83,7 +83,7 @@
* Bootloader initialized system infrastructure clock for * Bootloader initialized system infrastructure clock for
* serial devices. * serial devices.
*/ */
clk_ext2f_a9: clockgen-c0@13 { clk_ext2f_a9: clockgen-c0 {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
clock-frequency = <200000000>; clock-frequency = <200000000>;
@ -260,7 +260,7 @@
clock-frequency = <0>; clock-frequency = <0>;
}; };
clockgen-d2@x9106000 { clockgen-d2@9106000 {
compatible = "st,clkgen-c32"; compatible = "st,clkgen-c32";
reg = <0x9106000 0x1000>; reg = <0x9106000 0x1000>;

8
arch/arm/boot/dts/stih407-family.dtsi
View File

@ -92,7 +92,7 @@
clocks = <&arm_periph_clk>; clocks = <&arm_periph_clk>;
}; };
l2: cache-controller { l2: cache-controller@8762000 {
compatible = "arm,pl310-cache"; compatible = "arm,pl310-cache";
reg = <0x08762000 0x1000>; reg = <0x08762000 0x1000>;
arm,data-latency = <3 3 3>; arm,data-latency = <3 3 3>;
@ -389,7 +389,7 @@
reset-names = "global", "port"; reset-names = "global", "port";
}; };
miphy28lp_phy: miphy28lp@9b22000 { miphy28lp_phy: miphy28lp {
compatible = "st,miphy28lp-phy"; compatible = "st,miphy28lp-phy";
st,syscfg = <&syscfg_core>; st,syscfg = <&syscfg_core>;
#address-cells = <1>; #address-cells = <1>;
@ -803,7 +803,7 @@
status = "okay"; status = "okay";
}; };
st231_gp0: st231-gp0@0 { st231_gp0: st231-gp0 {
compatible = "st,st231-rproc"; compatible = "st,st231-rproc";
memory-region = <&gp0_reserved>; memory-region = <&gp0_reserved>;
resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
@ -816,7 +816,7 @@
mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>; mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
}; };
st231_delta: st231-delta@0 { st231_delta: st231-delta {
compatible = "st,st231-rproc"; compatible = "st,st231-rproc";
memory-region = <&delta_reserved>; memory-region = <&delta_reserved>;
resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;

10
arch/arm/boot/dts/stih407-pinctrl.dtsi
View File

@ -45,7 +45,7 @@
}; };
soc { soc {
pin-controller-sbc { pin-controller-sbc@961f080 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "st,stih407-sbc-pinctrl"; compatible = "st,stih407-sbc-pinctrl";
@ -369,7 +369,7 @@
}; };
}; };
pin-controller-front0 { pin-controller-front0@920f080 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "st,stih407-front-pinctrl"; compatible = "st,stih407-front-pinctrl";
@ -929,7 +929,7 @@
}; };
}; };
pin-controller-front1 { pin-controller-front1@921f080 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "st,stih407-front-pinctrl"; compatible = "st,stih407-front-pinctrl";
@ -962,7 +962,7 @@
}; };
}; };
pin-controller-rear { pin-controller-rear@922f080 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "st,stih407-rear-pinctrl"; compatible = "st,stih407-rear-pinctrl";
@ -1157,7 +1157,7 @@
}; };
}; };
pin-controller-flash { pin-controller-flash@923f080 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "st,stih407-flash-pinctrl"; compatible = "st,stih407-flash-pinctrl";

2
arch/arm/boot/dts/stih410-b2120.dts
View File

@ -18,7 +18,7 @@
linux,stdout-path = &sbc_serial0; linux,stdout-path = &sbc_serial0;
}; };
memory { memory@40000000 {
device_type = "memory"; device_type = "memory";
reg = <0x40000000 0x80000000>; reg = <0x40000000 0x80000000>;
}; };

4
arch/arm/boot/dts/stih410-b2260.dts
View File

@ -19,7 +19,7 @@
linux,stdout-path = &uart1; linux,stdout-path = &uart1;
}; };
memory { memory@40000000 {
device_type = "memory"; device_type = "memory";
reg = <0x40000000 0x40000000>; reg = <0x40000000 0x40000000>;
}; };
@ -201,7 +201,7 @@
}; };
}; };
miphy28lp_phy: miphy28lp@9b22000 { miphy28lp_phy: miphy28lp {
phy_port1: port@9b2a000 { phy_port1: port@9b2a000 {
st,osc-force-ext; st,osc-force-ext;

4
arch/arm/boot/dts/stih410-clock.dtsi
View File

@ -85,7 +85,7 @@
* Bootloader initialized system infrastructure clock for * Bootloader initialized system infrastructure clock for
* serial devices. * serial devices.
*/ */
clk_ext2f_a9: clockgen-c0@13 { clk_ext2f_a9: clockgen-c0 {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
clock-frequency = <200000000>; clock-frequency = <200000000>;
@ -272,7 +272,7 @@
clock-frequency = <0>; clock-frequency = <0>;
}; };
clockgen-d2@x9106000 { clockgen-d2@9106000 {
compatible = "st,clkgen-c32"; compatible = "st,clkgen-c32";
reg = <0x9106000 0x1000>; reg = <0x9106000 0x1000>;

2
arch/arm/boot/dts/stih410-pinctrl.dtsi
View File

@ -10,7 +10,7 @@
/ { / {
soc { soc {
pin-controller-rear { pin-controller-rear@922f080 {
usb0 { usb0 {
pinctrl_usb0: usb2-0 { pinctrl_usb0: usb2-0 {

2
arch/arm/boot/dts/stih410.dtsi
View File

@ -235,7 +235,7 @@
<&clk_s_d2_quadfs 1>; <&clk_s_d2_quadfs 1>;
}; };
sti-hqvdp@9c000000 { sti-hqvdp@9c00000 {
compatible = "st,stih407-hqvdp"; compatible = "st,stih407-hqvdp";
reg = <0x9C00000 0x100000>; reg = <0x9C00000 0x100000>;
clock-names = "hqvdp", "pix_main"; clock-names = "hqvdp", "pix_main";

4
arch/arm/boot/dts/stih418-b2199.dts
View File

@ -18,7 +18,7 @@
linux,stdout-path = &sbc_serial0; linux,stdout-path = &sbc_serial0;
}; };
memory { memory@40000000 {
device_type = "memory"; device_type = "memory";
reg = <0x40000000 0xc0000000>; reg = <0x40000000 0xc0000000>;
}; };
@ -88,7 +88,7 @@
non-removable; non-removable;
}; };
miphy28lp_phy: miphy28lp@9b22000 { miphy28lp_phy: miphy28lp {
phy_port0: port@9b22000 { phy_port0: port@9b22000 {
st,osc-rdy; st,osc-rdy;

4
arch/arm/boot/dts/stih418-clock.dtsi
View File

@ -85,7 +85,7 @@
* Bootloader initialized system infrastructure clock for * Bootloader initialized system infrastructure clock for
* serial devices. * serial devices.
*/ */
clk_ext2f_a9: clockgen-c0@13 { clk_ext2f_a9: clockgen-c0 {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
clock-frequency = <200000000>; clock-frequency = <200000000>;
@ -265,7 +265,7 @@
clock-frequency = <0>; clock-frequency = <0>;
}; };
clockgen-d2@x9106000 { clockgen-d2@9106000 {
compatible = "st,clkgen-c32"; compatible = "st,clkgen-c32";
reg = <0x9106000 0x1000>; reg = <0x9106000 0x1000>;

4
arch/arm/boot/dts/stihxxx-b2120.dtsi
View File

@ -80,7 +80,7 @@
st,i2c-min-sda-pulse-width-us = <5>; st,i2c-min-sda-pulse-width-us = <5>;
}; };
miphy28lp_phy: miphy28lp@9b22000 { miphy28lp_phy: miphy28lp {
phy_port0: port@9b22000 { phy_port0: port@9b22000 {
st,osc-rdy; st,osc-rdy;
@ -126,7 +126,7 @@
clock-names = "c8sectpfe"; clock-names = "c8sectpfe";
/* tsin0 is TSA on NIMA */ /* tsin0 is TSA on NIMA */
tsin0: port@0 { tsin0: port {
tsin-num = <0>; tsin-num = <0>;
serial-not-parallel; serial-not-parallel;
i2c-bus = <&ssc2>; i2c-bus = <&ssc2>;