forked from Minki/linux
net/mlx5: E-Switch, Introduce HCA cap and E-Switch vport context
E-Switch vport context is unlike NIC vport context, managed by the E-Switch manager or vport_group_manager and not by the NIC(VF) driver. The E-Switch manager can access (read/modify) any of its vports E-Switch context. Currently E-Switch vport context includes only clietnt and server vlan insertion and striping data (for later support of VST mode). Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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77256579c6
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@ -173,6 +173,17 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
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return err;
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}
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if (MLX5_CAP_GEN(dev, vport_group_manager)) {
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err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH,
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HCA_CAP_OPMOD_GET_CUR);
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if (err)
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return err;
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err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH,
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HCA_CAP_OPMOD_GET_MAX);
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if (err)
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return err;
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}
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return 0;
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}
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@ -1145,6 +1145,7 @@ enum mlx5_cap_type {
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MLX5_CAP_EOIB_OFFLOADS,
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MLX5_CAP_FLOW_TABLE,
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MLX5_CAP_ESWITCH_FLOW_TABLE,
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MLX5_CAP_ESWITCH,
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/* NUM OF CAP Types */
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MLX5_CAP_NUM
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};
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@ -1196,6 +1197,14 @@ enum mlx5_cap_type {
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#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
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MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
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#define MLX5_CAP_ESW(mdev, cap) \
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MLX5_GET(e_switch_cap, \
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mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
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#define MLX5_CAP_ESW_MAX(mdev, cap) \
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MLX5_GET(e_switch_cap, \
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mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
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#define MLX5_CAP_ODP(mdev, cap)\
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MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
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@ -459,6 +459,17 @@ struct mlx5_ifc_flow_table_eswitch_cap_bits {
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u8 reserved_1[0x7800];
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};
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struct mlx5_ifc_e_switch_cap_bits {
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u8 vport_svlan_strip[0x1];
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u8 vport_cvlan_strip[0x1];
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u8 vport_svlan_insert[0x1];
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u8 vport_cvlan_insert_if_not_exist[0x1];
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u8 vport_cvlan_insert_overwrite[0x1];
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u8 reserved_0[0x1b];
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u8 reserved_1[0x7e0];
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};
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struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
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u8 csum_cap[0x1];
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u8 vlan_cap[0x1];
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@ -1860,6 +1871,7 @@ union mlx5_ifc_hca_cap_union_bits {
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struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
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struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
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struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
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struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
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u8 reserved_0[0x8000];
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};
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@ -2305,6 +2317,26 @@ struct mlx5_ifc_hca_vport_context_bits {
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u8 reserved_6[0xca0];
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};
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struct mlx5_ifc_esw_vport_context_bits {
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u8 reserved_0[0x3];
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u8 vport_svlan_strip[0x1];
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u8 vport_cvlan_strip[0x1];
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u8 vport_svlan_insert[0x1];
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u8 vport_cvlan_insert[0x2];
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u8 reserved_1[0x18];
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u8 reserved_2[0x20];
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u8 svlan_cfi[0x1];
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u8 svlan_pcp[0x3];
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u8 svlan_id[0xc];
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u8 cvlan_cfi[0x1];
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u8 cvlan_pcp[0x3];
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u8 cvlan_id[0xc];
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u8 reserved_3[0x7a0];
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};
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enum {
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MLX5_EQC_STATUS_OK = 0x0,
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MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
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@ -3743,6 +3775,64 @@ struct mlx5_ifc_query_flow_group_in_bits {
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u8 reserved_5[0x120];
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};
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struct mlx5_ifc_query_esw_vport_context_out_bits {
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u8 status[0x8];
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u8 reserved_0[0x18];
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u8 syndrome[0x20];
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u8 reserved_1[0x40];
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struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
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};
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struct mlx5_ifc_query_esw_vport_context_in_bits {
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u8 opcode[0x10];
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u8 reserved_0[0x10];
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u8 reserved_1[0x10];
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u8 op_mod[0x10];
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u8 other_vport[0x1];
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u8 reserved_2[0xf];
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u8 vport_number[0x10];
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u8 reserved_3[0x20];
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};
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struct mlx5_ifc_modify_esw_vport_context_out_bits {
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u8 status[0x8];
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u8 reserved_0[0x18];
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u8 syndrome[0x20];
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u8 reserved_1[0x40];
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};
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struct mlx5_ifc_esw_vport_context_fields_select_bits {
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u8 reserved[0x1c];
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u8 vport_cvlan_insert[0x1];
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u8 vport_svlan_insert[0x1];
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u8 vport_cvlan_strip[0x1];
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u8 vport_svlan_strip[0x1];
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};
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struct mlx5_ifc_modify_esw_vport_context_in_bits {
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u8 opcode[0x10];
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u8 reserved_0[0x10];
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u8 reserved_1[0x10];
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u8 op_mod[0x10];
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u8 other_vport[0x1];
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u8 reserved_2[0xf];
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u8 vport_number[0x10];
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struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
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struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
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};
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struct mlx5_ifc_query_eq_out_bits {
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u8 status[0x8];
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u8 reserved_0[0x18];
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