Merge tag 'iommu-updates-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu updates from Joerg Roedel:
- ARM SMMU and Mediatek updates from Will Deacon:
- Support for MT8192 IOMMU from Mediatek
- Arm v7s io-pgtable extensions for MT8192
- Removal of TLBI_ON_MAP quirk
- New Qualcomm compatible strings
- Allow SVA without hardware broadcast TLB maintenance on SMMUv3
- Virtualization Host Extension support for SMMUv3 (SVA)
- Allow SMMUv3 PMU perf driver to be built independently from IOMMU
- Some tidy-up in IOVA and core code
- Conversion of the AMD IOMMU code to use the generic IO-page-table
framework
- Intel VT-d updates from Lu Baolu:
- Audit capability consistency among different IOMMUs
- Add SATC reporting structure support
- Add iotlb_sync_map callback support
- SDHI support for Renesas IOMMU driver
- Misc cleanups and other small improvments
* tag 'iommu-updates-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (94 commits)
iommu/amd: Fix performance counter initialization
MAINTAINERS: repair file pattern in MEDIATEK IOMMU DRIVER
iommu/mediatek: Fix error code in probe()
iommu/mediatek: Fix unsigned domid comparison with less than zero
iommu/vt-d: Parse SATC reporting structure
iommu/vt-d: Add new enum value and structure for SATC
iommu/vt-d: Add iotlb_sync_map callback
iommu/vt-d: Move capability check code to cap_audit files
iommu/vt-d: Audit IOMMU Capabilities and add helper functions
iommu/vt-d: Fix 'physical' typos
iommu: Properly pass gfp_t in _iommu_map() to avoid atomic sleeping
iommu/vt-d: Fix compile error [-Werror=implicit-function-declaration]
driver/perf: Remove ARM_SMMU_V3_PMU dependency on ARM_SMMU_V3
MAINTAINERS: Add entry for MediaTek IOMMU
iommu/mediatek: Add mt8192 support
iommu/mediatek: Remove unnecessary check in attach_device
iommu/mediatek: Support master use iova over 32bit
iommu/mediatek: Add iova reserved function
iommu/mediatek: Support for multi domains
iommu/mediatek: Add get_domain_id from dev->dma_range_map
...
This commit is contained in:
@@ -6,7 +6,6 @@
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*
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* Author: Lu Baolu <baolu.lu@linux.intel.com>
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*/
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#ifdef CONFIG_INTEL_IOMMU
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#undef TRACE_SYSTEM
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#define TRACE_SYSTEM intel_iommu
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@@ -135,8 +134,44 @@ DEFINE_EVENT(dma_map_sg, bounce_map_sg,
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struct scatterlist *sg),
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TP_ARGS(dev, index, total, sg)
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);
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TRACE_EVENT(qi_submit,
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TP_PROTO(struct intel_iommu *iommu, u64 qw0, u64 qw1, u64 qw2, u64 qw3),
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TP_ARGS(iommu, qw0, qw1, qw2, qw3),
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TP_STRUCT__entry(
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__field(u64, qw0)
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__field(u64, qw1)
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__field(u64, qw2)
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__field(u64, qw3)
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__string(iommu, iommu->name)
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),
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TP_fast_assign(
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__assign_str(iommu, iommu->name);
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__entry->qw0 = qw0;
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__entry->qw1 = qw1;
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__entry->qw2 = qw2;
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__entry->qw3 = qw3;
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),
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TP_printk("%s %s: 0x%llx 0x%llx 0x%llx 0x%llx",
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__print_symbolic(__entry->qw0 & 0xf,
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{ QI_CC_TYPE, "cc_inv" },
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{ QI_IOTLB_TYPE, "iotlb_inv" },
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{ QI_DIOTLB_TYPE, "dev_tlb_inv" },
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{ QI_IEC_TYPE, "iec_inv" },
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{ QI_IWD_TYPE, "inv_wait" },
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{ QI_EIOTLB_TYPE, "p_iotlb_inv" },
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{ QI_PC_TYPE, "pc_inv" },
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{ QI_DEIOTLB_TYPE, "p_dev_tlb_inv" },
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{ QI_PGRP_RESP_TYPE, "page_grp_resp" }),
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__get_str(iommu),
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__entry->qw0, __entry->qw1, __entry->qw2, __entry->qw3
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)
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);
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#endif /* _TRACE_INTEL_IOMMU_H */
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/* This part must be outside protection */
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#include <trace/define_trace.h>
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#endif /* CONFIG_INTEL_IOMMU */
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