forked from Minki/linux
drm/amdgpu/sriov:fix memory leak after gpu reset
GPU reset will require all hw doing hw_init thus ucode_init_bo will be invoked again, which lead to memory leak skip the fw_buf allocation during sriov gpu reset to avoid memory leak. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1187,6 +1187,9 @@ struct amdgpu_firmware {
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/* gpu info firmware data pointer */
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const struct firmware *gpu_info_fw;
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void *fw_buf_ptr;
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uint64_t fw_buf_mc;
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};
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/*
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@ -360,8 +360,6 @@ static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
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int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
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{
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struct amdgpu_bo **bo = &adev->firmware.fw_buf;
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uint64_t fw_mc_addr;
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void *fw_buf_ptr = NULL;
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uint64_t fw_offset = 0;
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int i, err;
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struct amdgpu_firmware_info *ucode = NULL;
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@ -372,6 +370,7 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
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return 0;
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}
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if (!amdgpu_sriov_vf(adev) || !adev->in_sriov_reset) {
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err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true,
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amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
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AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
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@ -388,21 +387,22 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
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}
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err = amdgpu_bo_pin(*bo, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
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&fw_mc_addr);
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&adev->firmware.fw_buf_mc);
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if (err) {
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dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err);
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goto failed_pin;
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}
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err = amdgpu_bo_kmap(*bo, &fw_buf_ptr);
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err = amdgpu_bo_kmap(*bo, &adev->firmware.fw_buf_ptr);
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if (err) {
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dev_err(adev->dev, "(%d) Firmware buffer kmap failed\n", err);
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goto failed_kmap;
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}
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amdgpu_bo_unreserve(*bo);
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}
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memset(fw_buf_ptr, 0, adev->firmware.fw_size);
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memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
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/*
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* if SMU loaded firmware, it needn't add SMC, UVD, and VCE
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@ -421,14 +421,14 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
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ucode = &adev->firmware.ucode[i];
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if (ucode->fw) {
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header = (const struct common_firmware_header *)ucode->fw->data;
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amdgpu_ucode_init_single_fw(adev, ucode, fw_mc_addr + fw_offset,
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(void *)((uint8_t *)fw_buf_ptr + fw_offset));
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amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
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adev->firmware.fw_buf_ptr + fw_offset);
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if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
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adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
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const struct gfx_firmware_header_v1_0 *cp_hdr;
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cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
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amdgpu_ucode_patch_jt(ucode, fw_mc_addr + fw_offset,
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fw_buf_ptr + fw_offset);
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amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset,
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adev->firmware.fw_buf_ptr + fw_offset);
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fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
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}
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fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
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