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riscv: Improve stack randomisation on RV64

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This enlarges the bits availiable for stack randomisation on RV64 from
the default of 8MiB to 1GiB, to match arm64 and x86.

Also, update the documentation to reflect our support for stack
randomisation.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
[Palmer: commit text]
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Kefeng Wang 2021-08-12 19:47:02 +08:00 committed by Palmer Dabbelt
parent efe1e08bca
commit d5935537c8
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GPG Key ID: 2E1319F35FBB1889
2 changed files with 4 additions and 1 deletions
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2
Documentation/features/vm/ELF-ASLR/arch-support.txt
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@ -22,7 +22,7 @@
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | ok | | parisc: | ok |
| powerpc: | ok | | powerpc: | ok |
| riscv: | TODO | | riscv: | ok |
| s390: | ok | | s390: | ok |
| sh: | TODO | | sh: | TODO |
| sparc: | TODO | | sparc: | TODO |

3
arch/riscv/include/asm/elf.h
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@ -42,6 +42,9 @@
*/ */
#define ELF_ET_DYN_BASE ((TASK_SIZE / 3) * 2) #define ELF_ET_DYN_BASE ((TASK_SIZE / 3) * 2)
#ifdef CONFIG_64BIT
#define STACK_RND_MASK (0x3ffff >> (PAGE_SHIFT - 12))
#endif
/* /*
* This yields a mask that user programs can use to figure out what * This yields a mask that user programs can use to figure out what
* instruction set this CPU supports. This could be done in user space, * instruction set this CPU supports. This could be done in user space,