Merge drm/drm-next into drm-intel-next
Sync up with topic/i915-gem-next and drm-intel-gt-next. Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula
commit
d527353e4b
@ -567,6 +567,24 @@ For printing netdev_features_t.
|
||||
|
||||
Passed by reference.
|
||||
|
||||
V4L2 and DRM FourCC code (pixel format)
|
||||
---------------------------------------
|
||||
|
||||
::
|
||||
|
||||
%p4cc
|
||||
|
||||
Print a FourCC code used by V4L2 or DRM, including format endianness and
|
||||
its numerical value as hexadecimal.
|
||||
|
||||
Passed by reference.
|
||||
|
||||
Examples::
|
||||
|
||||
%p4cc BG12 little-endian (0x32314742)
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||||
%p4cc Y10 little-endian (0x20303159)
|
||||
%p4cc NV12 big-endian (0xb231564e)
|
||||
|
||||
Thanks
|
||||
======
|
||||
|
||||
|
||||
@ -12,8 +12,8 @@ description: |
|
||||
and CEC.
|
||||
|
||||
These DT bindings follow the Synopsys DWC HDMI TX bindings defined
|
||||
in Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with
|
||||
the following device-specific properties.
|
||||
in bridge/synopsys,dw-hdmi.yaml with the following device-specific
|
||||
properties.
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||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
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|
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@ -109,7 +109,7 @@ required:
|
||||
- resets
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||||
- ddc
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|
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additionalProperties: false
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unevaluatedProperties: false
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||||
|
||||
examples:
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||||
- |
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||||
|
||||
@ -34,6 +34,15 @@ properties:
|
||||
description: used for reset chip control, RESET_N pin B7.
|
||||
maxItems: 1
|
||||
|
||||
vdd10-supply:
|
||||
description: Regulator that provides the supply 1.0V power.
|
||||
|
||||
vdd18-supply:
|
||||
description: Regulator that provides the supply 1.8V power.
|
||||
|
||||
vdd33-supply:
|
||||
description: Regulator that provides the supply 3.3V power.
|
||||
|
||||
ports:
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||||
$ref: /schemas/graph.yaml#/properties/ports
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||||
|
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@ -55,6 +64,9 @@ properties:
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||||
required:
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- compatible
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- reg
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- vdd10-supply
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- vdd18-supply
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- vdd33-supply
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||||
- ports
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|
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additionalProperties: false
|
||||
@ -72,6 +84,9 @@ examples:
|
||||
reg = <0x58>;
|
||||
enable-gpios = <&pio 45 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&pio 73 GPIO_ACTIVE_HIGH>;
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||||
vdd10-supply = <&pp1000_mipibrdg>;
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vdd18-supply = <&pp1800_mipibrdg>;
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vdd33-supply = <&pp3300_mipibrdg>;
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|
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ports {
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#address-cells = <1>;
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|
||||
@ -0,0 +1,99 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/chipone,icn6211.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge
|
||||
|
||||
maintainers:
|
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- Jagan Teki <jagan@amarulasolutions.com>
|
||||
|
||||
description: |
|
||||
ICN6211 is MIPI-DSI to RGB Converter bridge from chipone.
|
||||
|
||||
It has a flexible configuration of MIPI DSI signal input and
|
||||
produce RGB565, RGB666, RGB888 output format.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- chipone,icn6211
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: virtual channel number of a DSI peripheral
|
||||
|
||||
enable-gpios:
|
||||
description: Bridge EN pin, chip is reset when EN is low.
|
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|
||||
vdd1-supply:
|
||||
description: A 1.8V/2.5V/3.3V supply that power the MIPI RX.
|
||||
|
||||
vdd2-supply:
|
||||
description: A 1.8V/2.5V/3.3V supply that power the PLL.
|
||||
|
||||
vdd3-supply:
|
||||
description: A 1.8V/2.5V/3.3V supply that power the RGB output.
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
Video port for MIPI DSI input
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
Video port for MIPI DPI output (panel or connector).
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- enable-gpios
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
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||||
|
||||
dsi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
bridge@0 {
|
||||
compatible = "chipone,icn6211";
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||||
reg = <0>;
|
||||
enable-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* LCD-RST: PL5 */
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
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||||
|
||||
port@0 {
|
||||
reg = <0>;
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||||
|
||||
bridge_in_dsi: endpoint {
|
||||
remote-endpoint = <&dsi_out_bridge>;
|
||||
};
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||||
};
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||||
port@1 {
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reg = <1>;
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||||
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bridge_out_panel: endpoint {
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||||
remote-endpoint = <&panel_out_bridge>;
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||||
};
|
||||
};
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||||
};
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||||
};
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};
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@ -1,33 +0,0 @@
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Synopsys DesignWare HDMI TX Encoder
|
||||
===================================
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||||
|
||||
This document defines device tree properties for the Synopsys DesignWare HDMI
|
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TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
|
||||
specification by itself but is meant to be referenced by platform-specific
|
||||
device tree bindings.
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||||
|
||||
When referenced from platform device tree bindings the properties defined in
|
||||
this document are defined as follows. The platform device tree bindings are
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||||
responsible for defining whether each property is required or optional.
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||||
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||||
- reg: Memory mapped base address and length of the DWC HDMI TX registers.
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||||
|
||||
- reg-io-width: Width of the registers specified by the reg property. The
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value is expressed in bytes and must be equal to 1 or 4 if specified. The
|
||||
register width defaults to 1 if the property is not present.
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||||
|
||||
- interrupts: Reference to the DWC HDMI TX interrupt.
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||||
|
||||
- clocks: References to all the clocks specified in the clock-names property
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||||
as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt.
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||||
|
||||
- clock-names: The DWC HDMI TX uses the following clocks.
|
||||
|
||||
- "iahb" is the bus clock for either AHB and APB (mandatory).
|
||||
- "isfr" is the internal register configuration clock (mandatory).
|
||||
- "cec" is the HDMI CEC controller main clock (optional).
|
||||
|
||||
- ports: The connectivity of the DWC HDMI TX with the rest of the system is
|
||||
expressed in using ports as specified in the device graph bindings defined
|
||||
in Documentation/devicetree/bindings/graph.txt. The numbering of the ports
|
||||
is platform-specific.
|
||||
@ -0,0 +1,102 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/lontium,lt8912b.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Lontium LT8912B MIPI to HDMI Bridge
|
||||
|
||||
maintainers:
|
||||
- Adrien Grassein <adrien.grassein@gmail.com>
|
||||
|
||||
description: |
|
||||
The LT8912B is a bridge device which convert DSI to HDMI
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- lontium,lt8912b
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO connected to active high RESET pin.
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
Primary MIPI port for MIPI input
|
||||
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/media/video-interfaces.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
data-lanes: true
|
||||
|
||||
required:
|
||||
- data-lanes
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: |
|
||||
HDMI port, should be connected to a node compatible with the
|
||||
hdmi-connector binding.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reset-gpios
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
i2c4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hdmi-bridge@48 {
|
||||
compatible = "lontium,lt8912b";
|
||||
reg = <0x48>;
|
||||
reset-gpios = <&max7323 0 GPIO_ACTIVE_LOW>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
hdmi_out_in: endpoint {
|
||||
data-lanes = <0 1 2 3>;
|
||||
remote-endpoint = <&mipi_dsi_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&hdmi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -1,88 +0,0 @@
|
||||
Renesas Gen3 DWC HDMI TX Encoder
|
||||
================================
|
||||
|
||||
The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
|
||||
with a companion PHY IP.
|
||||
|
||||
These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
|
||||
Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
|
||||
following device-specific properties.
|
||||
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Shall contain one or more of
|
||||
- "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX
|
||||
- "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX
|
||||
- "renesas,r8a774e1-hdmi" for R8A774E1 (RZ/G2H) compatible HDMI TX
|
||||
- "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
|
||||
- "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
|
||||
- "renesas,r8a77961-hdmi" for R8A77961 (R-Car M3-W+) compatible HDMI TX
|
||||
- "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
|
||||
- "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 and RZ/G2 compatible
|
||||
HDMI TX
|
||||
|
||||
When compatible with generic versions, nodes must list the SoC-specific
|
||||
version corresponding to the platform first, followed by the
|
||||
family-specific version.
|
||||
|
||||
- reg: See dw_hdmi.txt.
|
||||
- interrupts: HDMI interrupt number
|
||||
- clocks: See dw_hdmi.txt.
|
||||
- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
|
||||
- ports: See dw_hdmi.txt. The DWC HDMI shall have one port numbered 0
|
||||
corresponding to the video input of the controller and one port numbered 1
|
||||
corresponding to its HDMI output, and one port numbered 2 corresponding to
|
||||
sound input of the controller. Each port shall have a single endpoint.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- power-domains: Shall reference the power domain that contains the DWC HDMI,
|
||||
if any.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
hdmi0: hdmi@fead0000 {
|
||||
compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
|
||||
reg = <0 0xfead0000 0 0x10000>;
|
||||
interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
|
||||
clock-names = "iahb", "isfr";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dw_hdmi0_in: endpoint {
|
||||
remote-endpoint = <&du_out_hdmi0>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
rcar_dw_hdmi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
rcar_dw_hdmi0_sound_in: endpoint {
|
||||
remote-endpoint = <&hdmi_sound_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi0-out {
|
||||
compatible = "hdmi-connector";
|
||||
label = "HDMI0 OUT";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi0_con: endpoint {
|
||||
remote-endpoint = <&rcar_dw_hdmi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,125 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/renesas,dw-hdmi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas R-Car DWC HDMI TX Encoder
|
||||
|
||||
maintainers:
|
||||
- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
|
||||
|
||||
description: |
|
||||
The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
|
||||
with a companion PHY IP.
|
||||
|
||||
allOf:
|
||||
- $ref: synopsys,dw-hdmi.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,r8a774a1-hdmi # for RZ/G2M compatible HDMI TX
|
||||
- renesas,r8a774b1-hdmi # for RZ/G2N compatible HDMI TX
|
||||
- renesas,r8a774e1-hdmi # for RZ/G2H compatible HDMI TX
|
||||
- renesas,r8a7795-hdmi # for R-Car H3 compatible HDMI TX
|
||||
- renesas,r8a7796-hdmi # for R-Car M3-W compatible HDMI TX
|
||||
- renesas,r8a77961-hdmi # for R-Car M3-W+ compatible HDMI TX
|
||||
- renesas,r8a77965-hdmi # for R-Car M3-N compatible HDMI TX
|
||||
- const: renesas,rcar-gen3-hdmi
|
||||
|
||||
reg-io-width:
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
maxItems: 2
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Parallel RGB input port
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: HDMI output port
|
||||
|
||||
port@2:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Sound input port
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
- port@2
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- interrupts
|
||||
- ports
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/power/r8a7795-sysc.h>
|
||||
|
||||
hdmi@fead0000 {
|
||||
compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
|
||||
reg = <0xfead0000 0x10000>;
|
||||
interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
|
||||
clock-names = "iahb", "isfr";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dw_hdmi0_in: endpoint {
|
||||
remote-endpoint = <&du_out_hdmi0>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
rcar_dw_hdmi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
rcar_dw_hdmi0_sound_in: endpoint {
|
||||
remote-endpoint = <&hdmi_sound_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi0-out {
|
||||
compatible = "hdmi-connector";
|
||||
label = "HDMI0 OUT";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi0_con: endpoint {
|
||||
remote-endpoint = <&rcar_dw_hdmi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -0,0 +1,55 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Common Properties for Synopsys DesignWare HDMI TX Controller
|
||||
|
||||
maintainers:
|
||||
- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
|
||||
|
||||
description: |
|
||||
This document defines device tree properties for the Synopsys DesignWare HDMI
|
||||
TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
|
||||
binding specification by itself but is meant to be referenced by device tree
|
||||
bindings for the platform-specific integrations of the DWC HDMI TX.
|
||||
|
||||
When referenced from platform device tree bindings the properties defined in
|
||||
this document are defined as follows. The platform device tree bindings are
|
||||
responsible for defining whether each property is required or optional.
|
||||
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reg-io-width:
|
||||
description:
|
||||
Width (in bytes) of the registers specified by the reg property.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [1, 4]
|
||||
default: 1
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 5
|
||||
items:
|
||||
- description: The bus clock for either AHB and APB
|
||||
- description: The internal register configuration clock
|
||||
additionalItems: true
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
maxItems: 5
|
||||
items:
|
||||
- const: iahb
|
||||
- const: isfr
|
||||
additionalItems: true
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
110
Documentation/devicetree/bindings/display/fsl,lcdif.yaml
Normal file
110
Documentation/devicetree/bindings/display/fsl,lcdif.yaml
Normal file
@ -0,0 +1,110 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/fsl,lcdif.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale/NXP i.MX LCD Interface (LCDIF)
|
||||
|
||||
maintainers:
|
||||
- Marek Vasut <marex@denx.de>
|
||||
- Stefan Agner <stefan@agner.ch>
|
||||
|
||||
description: |
|
||||
(e)LCDIF display controller found in the Freescale/NXP i.MX SoCs.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- fsl,imx23-lcdif
|
||||
- fsl,imx28-lcdif
|
||||
- fsl,imx6sx-lcdif
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,imx6sl-lcdif
|
||||
- fsl,imx6sll-lcdif
|
||||
- fsl,imx6ul-lcdif
|
||||
- fsl,imx7d-lcdif
|
||||
- fsl,imx8mm-lcdif
|
||||
- fsl,imx8mq-lcdif
|
||||
- const: fsl,imx6sx-lcdif
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Pixel clock
|
||||
- description: Bus clock
|
||||
- description: Display AXI clock
|
||||
minItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pix
|
||||
- const: axi
|
||||
- const: disp_axi
|
||||
minItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
port:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: The LCDIF output port
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- interrupts
|
||||
- port
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: fsl,imx6sx-lcdif
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
required:
|
||||
- clock-names
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 1
|
||||
clock-names:
|
||||
maxItems: 1
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx6sx-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
display-controller@2220000 {
|
||||
compatible = "fsl,imx6sx-lcdif";
|
||||
reg = <0x02220000 0x4000>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
|
||||
<&clks IMX6SX_CLK_LCDIF_APB>,
|
||||
<&clks IMX6SX_CLK_DISPLAY_AXI>;
|
||||
clock-names = "pix", "axi", "disp_axi";
|
||||
|
||||
port {
|
||||
endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
126
Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml
Normal file
126
Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml
Normal file
@ -0,0 +1,126 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/imx/fsl,imx6-hdmi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale i.MX6 DWC HDMI TX Encoder
|
||||
|
||||
maintainers:
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
|
||||
with a companion PHY IP.
|
||||
|
||||
allOf:
|
||||
- $ref: ../bridge/synopsys,dw-hdmi.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,imx6dl-hdmi
|
||||
- fsl,imx6q-hdmi
|
||||
|
||||
reg-io-width:
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
maxItems: 2
|
||||
|
||||
ddc-i2c-bus:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
The HDMI DDC bus can be connected to either a system I2C master or the
|
||||
functionally-reduced I2C master contained in the DWC HDMI. When connected
|
||||
to a system I2C master this property contains a phandle to that I2C
|
||||
master controller.
|
||||
|
||||
gpr:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
phandle to the iomuxc-gpr region containing the HDMI multiplexer control
|
||||
register.
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description: |
|
||||
This device has four video ports, corresponding to the four inputs of the
|
||||
HDMI multiplexer. Each port shall have a single endpoint.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: First input of the HDMI multiplexer
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Second input of the HDMI multiplexer
|
||||
|
||||
port@2:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Third input of the HDMI multiplexer
|
||||
|
||||
port@3:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Fourth input of the HDMI multiplexer
|
||||
|
||||
anyOf:
|
||||
- required:
|
||||
- port@0
|
||||
- required:
|
||||
- port@1
|
||||
- required:
|
||||
- port@2
|
||||
- required:
|
||||
- port@3
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- gpr
|
||||
- interrupts
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx6qdl-clock.h>
|
||||
|
||||
hdmi: hdmi@120000 {
|
||||
reg = <0x00120000 0x9000>;
|
||||
interrupts = <0 115 0x04>;
|
||||
gpr = <&gpr>;
|
||||
clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
|
||||
<&clks IMX6QDL_CLK_HDMI_ISFR>;
|
||||
clock-names = "iahb", "isfr";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
hdmi_mux_0: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
hdmi_mux_1: endpoint {
|
||||
remote-endpoint = <&ipu1_di1_hdmi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -1,65 +0,0 @@
|
||||
Freescale i.MX6 DWC HDMI TX Encoder
|
||||
===================================
|
||||
|
||||
The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
|
||||
with a companion PHY IP.
|
||||
|
||||
These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
|
||||
Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
|
||||
following device-specific properties.
|
||||
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
|
||||
- reg: See dw_hdmi.txt.
|
||||
- interrupts: HDMI interrupt number
|
||||
- clocks: See dw_hdmi.txt.
|
||||
- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
|
||||
- ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,
|
||||
numbered 0 to 3, corresponding to the four inputs of the HDMI multiplexer.
|
||||
Each port shall have a single endpoint.
|
||||
- gpr : Shall contain a phandle to the iomuxc-gpr region containing the HDMI
|
||||
multiplexer control register.
|
||||
|
||||
Optional properties
|
||||
|
||||
- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
|
||||
or the functionally-reduced I2C master contained in the DWC HDMI. When
|
||||
connected to a system I2C master this property contains a phandle to that
|
||||
I2C master controller.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
gpr: iomuxc-gpr@20e0000 {
|
||||
/* ... */
|
||||
};
|
||||
|
||||
hdmi: hdmi@120000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-hdmi";
|
||||
reg = <0x00120000 0x9000>;
|
||||
interrupts = <0 115 0x04>;
|
||||
gpr = <&gpr>;
|
||||
clocks = <&clks 123>, <&clks 124>;
|
||||
clock-names = "iahb", "isfr";
|
||||
ddc-i2c-bus = <&i2c2>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
hdmi_mux_0: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
hdmi_mux_1: endpoint {
|
||||
remote-endpoint = <&ipu1_di1_hdmi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -22,6 +22,7 @@ properties:
|
||||
- mediatek,mt7623-dpi
|
||||
- mediatek,mt8173-dpi
|
||||
- mediatek,mt8183-dpi
|
||||
- mediatek,mt8192-dpi
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -50,15 +51,10 @@ properties:
|
||||
- const: sleep
|
||||
|
||||
port:
|
||||
type: object
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
Output port node with endpoint definitions as described in
|
||||
Documentation/devicetree/bindings/graph.txt. This port should be connected
|
||||
to the input port of an attached HDMI or LVDS encoder chip.
|
||||
|
||||
properties:
|
||||
endpoint:
|
||||
type: object
|
||||
Output port node. This port should be connected to the input port of an
|
||||
attached HDMI or LVDS encoder chip.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -1,87 +0,0 @@
|
||||
* Freescale MXS LCD Interface (LCDIF)
|
||||
|
||||
New bindings:
|
||||
=============
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx23-lcdif" for i.MX23.
|
||||
Should be "fsl,imx28-lcdif" for i.MX28.
|
||||
Should be "fsl,imx6sx-lcdif" for i.MX6SX.
|
||||
Should be "fsl,imx8mq-lcdif" for i.MX8MQ.
|
||||
- reg: Address and length of the register set for LCDIF
|
||||
- interrupts: Should contain LCDIF interrupt
|
||||
- clocks: A list of phandle + clock-specifier pairs, one for each
|
||||
entry in 'clock-names'.
|
||||
- clock-names: A list of clock names. For MXSFB it should contain:
|
||||
- "pix" for the LCDIF block clock
|
||||
- (MX6SX-only) "axi", "disp_axi" for the bus interface clock
|
||||
|
||||
Required sub-nodes:
|
||||
- port: The connection to an encoder chip.
|
||||
|
||||
Example:
|
||||
|
||||
lcdif1: display-controller@2220000 {
|
||||
compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
|
||||
reg = <0x02220000 0x4000>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
|
||||
<&clks IMX6SX_CLK_LCDIF_APB>,
|
||||
<&clks IMX6SX_CLK_DISPLAY_AXI>;
|
||||
clock-names = "pix", "axi", "disp_axi";
|
||||
|
||||
port {
|
||||
parallel_out: endpoint {
|
||||
remote-endpoint = <&panel_in_parallel>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Deprecated bindings:
|
||||
====================
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx23-lcdif" for i.MX23.
|
||||
Should be "fsl,imx28-lcdif" for i.MX28.
|
||||
- reg: Address and length of the register set for LCDIF
|
||||
- interrupts: Should contain LCDIF interrupts
|
||||
- display: phandle to display node (see below for details)
|
||||
|
||||
* display node
|
||||
|
||||
Required properties:
|
||||
- bits-per-pixel: <16> for RGB565, <32> for RGB888/666.
|
||||
- bus-width: number of data lines. Could be <8>, <16>, <18> or <24>.
|
||||
|
||||
Required sub-node:
|
||||
- display-timings: Refer to binding doc display-timing.txt for details.
|
||||
|
||||
Examples:
|
||||
|
||||
lcdif@80030000 {
|
||||
compatible = "fsl,imx28-lcdif";
|
||||
reg = <0x80030000 2000>;
|
||||
interrupts = <38 86>;
|
||||
|
||||
display: display {
|
||||
bits-per-pixel = <32>;
|
||||
bus-width = <24>;
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: timing0 {
|
||||
clock-frequency = <33500000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hfront-porch = <164>;
|
||||
hback-porch = <89>;
|
||||
hsync-len = <10>;
|
||||
vback-porch = <23>;
|
||||
vfront-porch = <10>;
|
||||
vsync-len = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -161,6 +161,8 @@ properties:
|
||||
# Innolux Corporation 12.1" G121X1-L03 XGA (1024x768) TFT LCD panel
|
||||
- innolux,g121x1-l03
|
||||
# Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel
|
||||
- innolux,n116bca-ea1
|
||||
# Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel
|
||||
- innolux,n116bge
|
||||
# InnoLux 13.3" FHD (1920x1080) eDP TFT LCD panel
|
||||
- innolux,n125hce-gn1
|
||||
|
||||
@ -1,145 +0,0 @@
|
||||
* Renesas R-Car Display Unit (DU)
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: must be one of the following.
|
||||
- "renesas,du-r8a7742" for R8A7742 (RZ/G1H) compatible DU
|
||||
- "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU
|
||||
- "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU
|
||||
- "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU
|
||||
- "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU
|
||||
- "renesas,du-r8a774a1" for R8A774A1 (RZ/G2M) compatible DU
|
||||
- "renesas,du-r8a774b1" for R8A774B1 (RZ/G2N) compatible DU
|
||||
- "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU
|
||||
- "renesas,du-r8a774e1" for R8A774E1 (RZ/G2H) compatible DU
|
||||
- "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
|
||||
- "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
|
||||
- "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
|
||||
- "renesas,du-r8a7792" for R8A7792 (R-Car V2H) compatible DU
|
||||
- "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU
|
||||
- "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
|
||||
- "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
|
||||
- "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU
|
||||
- "renesas,du-r8a77961" for R8A77961 (R-Car M3-W+) compatible DU
|
||||
- "renesas,du-r8a77965" for R8A77965 (R-Car M3-N) compatible DU
|
||||
- "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU
|
||||
- "renesas,du-r8a77980" for R8A77980 (R-Car V3H) compatible DU
|
||||
- "renesas,du-r8a77990" for R8A77990 (R-Car E3) compatible DU
|
||||
- "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU
|
||||
|
||||
- reg: the memory-mapped I/O registers base address and length
|
||||
|
||||
- interrupts: Interrupt specifiers for the DU interrupts.
|
||||
|
||||
- clocks: A list of phandles + clock-specifier pairs, one for each entry in
|
||||
the clock-names property.
|
||||
- clock-names: Name of the clocks. This property is model-dependent.
|
||||
- R8A7779 uses a single functional clock. The clock doesn't need to be
|
||||
named.
|
||||
- All other DU instances use one functional clock per channel The
|
||||
functional clocks must be named "du.x" with "x" being the channel
|
||||
numerical index.
|
||||
- In addition to the functional clocks, all DU versions also support
|
||||
externally supplied pixel clocks. Those clocks are optional. When
|
||||
supplied they must be named "dclkin.x" with "x" being the input clock
|
||||
numerical index.
|
||||
|
||||
- renesas,cmms: A list of phandles to the CMM instances present in the SoC,
|
||||
one for each available DU channel. The property shall not be specified for
|
||||
SoCs that do not provide any CMM (such as V3M and V3H).
|
||||
|
||||
- renesas,vsps: A list of phandle and channel index tuples to the VSPs that
|
||||
handle the memory interfaces for the DU channels. The phandle identifies the
|
||||
VSP instance that serves the DU channel, and the channel index identifies
|
||||
the LIF instance in that VSP.
|
||||
|
||||
Optional properties:
|
||||
- resets: A list of phandle + reset-specifier pairs, one for each entry in
|
||||
the reset-names property.
|
||||
- reset-names: Names of the resets. This property is model-dependent.
|
||||
- All but R8A7779 use one reset for a group of one or more successive
|
||||
channels. The resets must be named "du.x" with "x" being the numerical
|
||||
index of the lowest channel in the group.
|
||||
|
||||
Required nodes:
|
||||
|
||||
The connections to the DU output video ports are modeled using the OF graph
|
||||
bindings specified in Documentation/devicetree/bindings/graph.txt.
|
||||
|
||||
The following table lists for each supported model the port number
|
||||
corresponding to each DU output.
|
||||
|
||||
Port0 Port1 Port2 Port3
|
||||
-----------------------------------------------------------------------------
|
||||
R8A7742 (RZ/G1H) DPAD 0 LVDS 0 LVDS 1 -
|
||||
R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - -
|
||||
R8A7744 (RZ/G1N) DPAD 0 LVDS 0 - -
|
||||
R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - -
|
||||
R8A77470 (RZ/G1C) DPAD 0 DPAD 1 LVDS 0 -
|
||||
R8A774A1 (RZ/G2M) DPAD 0 HDMI 0 LVDS 0 -
|
||||
R8A774B1 (RZ/G2N) DPAD 0 HDMI 0 LVDS 0 -
|
||||
R8A774C0 (RZ/G2E) DPAD 0 LVDS 0 LVDS 1 -
|
||||
R8A774E1 (RZ/G2H) DPAD 0 HDMI 0 LVDS 0 -
|
||||
R8A7779 (R-Car H1) DPAD 0 DPAD 1 - -
|
||||
R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 -
|
||||
R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - -
|
||||
R8A7792 (R-Car V2H) DPAD 0 DPAD 1 - -
|
||||
R8A7793 (R-Car M2-N) DPAD 0 LVDS 0 - -
|
||||
R8A7794 (R-Car E2) DPAD 0 DPAD 1 - -
|
||||
R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0
|
||||
R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 -
|
||||
R8A77961 (R-Car M3-W+) DPAD 0 HDMI 0 LVDS 0 -
|
||||
R8A77965 (R-Car M3-N) DPAD 0 HDMI 0 LVDS 0 -
|
||||
R8A77970 (R-Car V3M) DPAD 0 LVDS 0 - -
|
||||
R8A77980 (R-Car V3H) DPAD 0 LVDS 0 - -
|
||||
R8A77990 (R-Car E3) DPAD 0 LVDS 0 LVDS 1 -
|
||||
R8A77995 (R-Car D3) DPAD 0 LVDS 0 LVDS 1 -
|
||||
|
||||
|
||||
Example: R8A7795 (R-Car H3) ES2.0 DU
|
||||
|
||||
du: display@feb00000 {
|
||||
compatible = "renesas,du-r8a7795";
|
||||
reg = <0 0xfeb00000 0 0x80000>;
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 721>;
|
||||
clock-names = "du.0", "du.1", "du.2", "du.3";
|
||||
resets = <&cpg 724>, <&cpg 722>;
|
||||
reset-names = "du.0", "du.2";
|
||||
renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>;
|
||||
renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
du_out_hdmi0: endpoint {
|
||||
remote-endpoint = <&dw_hdmi0_in>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
du_out_hdmi1: endpoint {
|
||||
remote-endpoint = <&dw_hdmi1_in>;
|
||||
};
|
||||
};
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
du_out_lvds0: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
831
Documentation/devicetree/bindings/display/renesas,du.yaml
Normal file
831
Documentation/devicetree/bindings/display/renesas,du.yaml
Normal file
@ -0,0 +1,831 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/renesas,du.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas R-Car Display Unit (DU)
|
||||
|
||||
maintainers:
|
||||
- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
|
||||
|
||||
description: |
|
||||
These DT bindings describe the Display Unit embedded in the Renesas R-Car
|
||||
Gen1, R-Car Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- renesas,du-r8a7742 # for RZ/G1H compatible DU
|
||||
- renesas,du-r8a7743 # for RZ/G1M compatible DU
|
||||
- renesas,du-r8a7744 # for RZ/G1N compatible DU
|
||||
- renesas,du-r8a7745 # for RZ/G1E compatible DU
|
||||
- renesas,du-r8a77470 # for RZ/G1C compatible DU
|
||||
- renesas,du-r8a774a1 # for RZ/G2M compatible DU
|
||||
- renesas,du-r8a774b1 # for RZ/G2N compatible DU
|
||||
- renesas,du-r8a774c0 # for RZ/G2E compatible DU
|
||||
- renesas,du-r8a774e1 # for RZ/G2H compatible DU
|
||||
- renesas,du-r8a7779 # for R-Car H1 compatible DU
|
||||
- renesas,du-r8a7790 # for R-Car H2 compatible DU
|
||||
- renesas,du-r8a7791 # for R-Car M2-W compatible DU
|
||||
- renesas,du-r8a7792 # for R-Car V2H compatible DU
|
||||
- renesas,du-r8a7793 # for R-Car M2-N compatible DU
|
||||
- renesas,du-r8a7794 # for R-Car E2 compatible DU
|
||||
- renesas,du-r8a7795 # for R-Car H3 compatible DU
|
||||
- renesas,du-r8a7796 # for R-Car M3-W compatible DU
|
||||
- renesas,du-r8a77961 # for R-Car M3-W+ compatible DU
|
||||
- renesas,du-r8a77965 # for R-Car M3-N compatible DU
|
||||
- renesas,du-r8a77970 # for R-Car V3M compatible DU
|
||||
- renesas,du-r8a77980 # for R-Car V3H compatible DU
|
||||
- renesas,du-r8a77990 # for R-Car E3 compatible DU
|
||||
- renesas,du-r8a77995 # for R-Car D3 compatible DU
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
# See compatible-specific constraints below.
|
||||
clocks: true
|
||||
clock-names: true
|
||||
interrupts:
|
||||
description: Interrupt specifiers, one per DU channel
|
||||
resets: true
|
||||
reset-names: true
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: |
|
||||
The connections to the DU output video ports are modeled using the OF
|
||||
graph bindings specified in Documentation/devicetree/bindings/graph.txt.
|
||||
The number of ports and their assignment are model-dependent. Each port
|
||||
shall have a single endpoint.
|
||||
|
||||
patternProperties:
|
||||
"^port@[0-3]$":
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
renesas,cmms:
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle-array"
|
||||
description:
|
||||
A list of phandles to the CMM instances present in the SoC, one for each
|
||||
available DU channel.
|
||||
|
||||
renesas,vsps:
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle-array"
|
||||
description:
|
||||
A list of phandle and channel index tuples to the VSPs that handle the
|
||||
memory interfaces for the DU channels. The phandle identifies the VSP
|
||||
instance that serves the DU channel, and the channel index identifies
|
||||
the LIF instance in that VSP.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- interrupts
|
||||
- resets
|
||||
- ports
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,du-r8a7779
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
items:
|
||||
- description: Functional clock
|
||||
- description: DU_DOTCLKIN0 input clock
|
||||
- description: DU_DOTCLKIN1 input clock
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
items:
|
||||
- const: du.0
|
||||
- pattern: '^dclkin\.[01]$'
|
||||
- pattern: '^dclkin\.[01]$'
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
properties:
|
||||
port@0:
|
||||
description: DPAD 0
|
||||
port@1:
|
||||
description: DPAD 1
|
||||
# port@2 is TCON, not supported yet
|
||||
port@2: false
|
||||
port@3: false
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- interrupts
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,du-r8a7743
|
||||
- renesas,du-r8a7744
|
||||
- renesas,du-r8a7791
|
||||
- renesas,du-r8a7793
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
items:
|
||||
- description: Functional clock for DU0
|
||||
- description: Functional clock for DU1
|
||||
- description: DU_DOTCLKIN0 input clock
|
||||
- description: DU_DOTCLKIN1 input clock
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
items:
|
||||
- const: du.0
|
||||
- const: du.1
|
||||
- pattern: '^dclkin\.[01]$'
|
||||
- pattern: '^dclkin\.[01]$'
|
||||
|
||||
interrupts:
|
||||
maxItems: 2
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: du.0
|
||||
|
||||
ports:
|
||||
properties:
|
||||
port@0:
|
||||
description: DPAD 0
|
||||
port@1:
|
||||
description: LVDS 0
|
||||
# port@2 is TCON, not supported yet
|
||||
port@2: false
|
||||
port@3: false
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- clock-names
|
||||
- interrupts
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,du-r8a7745
|
||||
- renesas,du-r8a7792
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
items:
|
||||
- description: Functional clock for DU0
|
||||
- description: Functional clock for DU1
|
||||
- description: DU_DOTCLKIN0 input clock
|
||||
- description: DU_DOTCLKIN1 input clock
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
items:
|
||||
- const: du.0
|
||||
- const: du.1
|
||||
- pattern: '^dclkin\.[01]$'
|
||||
- pattern: '^dclkin\.[01]$'
|
||||
|
||||
interrupts:
|
||||
maxItems: 2
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: du.0
|
||||
|
||||
ports:
|
||||
properties:
|
||||
port@0:
|
||||
description: DPAD 0
|
||||
port@1:
|
||||
description: DPAD 1
|
||||
port@2: false
|
||||
port@3: false
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- clock-names
|
||||
- interrupts
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,du-r8a7794
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
items:
|
||||
- description: Functional clock for DU0
|
||||
- description: Functional clock for DU1
|
||||
- description: DU_DOTCLKIN0 input clock
|
||||
- description: DU_DOTCLKIN1 input clock
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
items:
|
||||
- const: du.0
|
||||
- const: du.1
|
||||
- pattern: '^dclkin\.[01]$'
|
||||
- pattern: '^dclkin\.[01]$'
|
||||
|
||||
interrupts:
|
||||
maxItems: 2
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: du.0
|
||||
|
||||
ports:
|
||||
properties:
|
||||
port@0:
|
||||
description: DPAD 0
|
||||
port@1:
|
||||
description: DPAD 1
|
||||
# port@2 is TCON, not supported yet
|
||||
port@2: false
|
||||
port@3: false
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- clock-names
|
||||
- interrupts
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,du-r8a77470
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
items:
|
||||
- description: Functional clock for DU0
|
||||
- description: Functional clock for DU1
|
||||
- description: DU_DOTCLKIN0 input clock
|
||||
- description: DU_DOTCLKIN1 input clock
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
items:
|
||||
- const: du.0
|
||||
- const: du.1
|
||||
- pattern: '^dclkin\.[01]$'
|
||||
- pattern: '^dclkin\.[01]$'
|
||||
|
||||
interrupts:
|
||||
maxItems: 2
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: du.0
|
||||
|
||||
ports:
|
||||
properties:
|
||||
port@0:
|
||||
description: DPAD 0
|
||||
port@1:
|
||||
description: DPAD 1
|
||||
port@2:
|
||||
description: LVDS 0
|
||||
# port@3 is DVENC, not supported yet
|
||||
port@3: false
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
- port@2
|
||||
|
||||
required:
|
||||
- clock-names
|
||||
- interrupts
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,du-r8a7742
|
||||
- renesas,du-r8a7790
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 6
|
||||
items:
|
||||
- description: Functional clock for DU0
|
||||
- description: Functional clock for DU1
|
||||
- description: Functional clock for DU2
|
||||
- description: DU_DOTCLKIN0 input clock
|
||||
- description: DU_DOTCLKIN1 input clock
|
||||
- description: DU_DOTCLKIN2 input clock
|
||||
|
||||
clock-names:
|
||||
minItems: 3
|
||||
maxItems: 6
|
||||
items:
|
||||
- const: du.0
|
||||
- const: du.1
|
||||
- const: du.2
|
||||
- pattern: '^dclkin\.[012]$'
|
||||
- pattern: '^dclkin\.[012]$'
|
||||
- pattern: '^dclkin\.[012]$'
|
||||
|
||||
interrupts:
|
||||
maxItems: 3
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: du.0
|
||||
|
||||
ports:
|
||||
properties:
|
||||
port@0:
|
||||
description: DPAD 0
|
||||
port@1:
|
||||
description: LVDS 0
|
||||
port@2:
|
||||
description: LVDS 1
|
||||
# port@3 is TCON, not supported yet
|
||||
port@3: false
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
- port@2
|
||||
|
||||
required:
|
||||
- clock-names
|
||||
- interrupts
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,du-r8a7795
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 8
|
||||
items:
|
||||
- description: Functional clock for DU0
|
||||
- description: Functional clock for DU1
|
||||
- description: Functional clock for DU2
|
||||
- description: Functional clock for DU4
|
||||
- description: DU_DOTCLKIN0 input clock
|
||||
- description: DU_DOTCLKIN1 input clock
|
||||
- description: DU_DOTCLKIN2 input clock
|
||||
- description: DU_DOTCLKIN3 input clock
|
||||
|
||||
clock-names:
|
||||
minItems: 4
|
||||
maxItems: 8
|
||||
items:
|
||||
- const: du.0
|
||||
- const: du.1
|
||||
- const: du.2
|
||||
- const: du.3
|
||||
- pattern: '^dclkin\.[0123]$'
|
||||
- pattern: '^dclkin\.[0123]$'
|
||||
- pattern: '^dclkin\.[0123]$'
|
||||
- pattern: '^dclkin\.[0123]$'
|
||||
|
||||
interrupts:
|
||||
maxItems: 4
|
||||
|
||||
resets:
|
||||
maxItems: 2
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: du.0
|
||||
- const: du.2
|
||||
|
||||
ports:
|
||||
properties:
|
||||
port@0:
|
||||
description: DPAD 0
|
||||
port@1:
|
||||
description: HDMI 0
|
||||
port@2:
|
||||
description: HDMI 1
|
||||
port@3:
|
||||
description: LVDS 0
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
- port@2
|
||||
- port@3
|
||||
|
||||
renesas,cmms:
|
||||
minItems: 4
|
||||
|
||||
renesas,vsps:
|
||||
minItems: 4
|
||||
|
||||
required:
|
||||
- clock-names
|
||||
- interrupts
|
||||
- resets
|
||||
- reset-names
|
||||
- renesas,vsps
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,du-r8a774a1
|
||||
- renesas,du-r8a7796
|
||||
- renesas,du-r8a77961
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 6
|
||||
items:
|
||||
- description: Functional clock for DU0
|
||||
- description: Functional clock for DU1
|
||||
- description: Functional clock for DU2
|
||||
- description: DU_DOTCLKIN0 input clock
|
||||
- description: DU_DOTCLKIN1 input clock
|
||||
- description: DU_DOTCLKIN2 input clock
|
||||
|
||||
clock-names:
|
||||
minItems: 3
|
||||
maxItems: 6
|
||||
items:
|
||||
- const: du.0
|
||||
- const: du.1
|
||||
- const: du.2
|
||||
- pattern: '^dclkin\.[012]$'
|
||||
- pattern: '^dclkin\.[012]$'
|
||||
- pattern: '^dclkin\.[012]$'
|
||||
|
||||
interrupts:
|
||||
maxItems: 3
|
||||
|
||||
resets:
|
||||
maxItems: 2
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: du.0
|
||||
- const: du.2
|
||||
|
||||
ports:
|
||||
properties:
|
||||
port@0:
|
||||
description: DPAD 0
|
||||
port@1:
|
||||
description: HDMI 0
|
||||
port@2:
|
||||
description: LVDS 0
|
||||
port@3: false
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
- port@2
|
||||
|
||||
renesas,cmms:
|
||||
minItems: 3
|
||||
|
||||
renesas,vsps:
|
||||
minItems: 3
|
||||
|
||||
required:
|
||||
- clock-names
|
||||
- interrupts
|
||||
- resets
|
||||
- reset-names
|
||||
- renesas,vsps
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,du-r8a774b1
|
||||
- renesas,du-r8a774e1
|
||||
- renesas,du-r8a77965
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 6
|
||||
items:
|
||||
- description: Functional clock for DU0
|
||||
- description: Functional clock for DU1
|
||||
- description: Functional clock for DU3
|
||||
- description: DU_DOTCLKIN0 input clock
|
||||
- description: DU_DOTCLKIN1 input clock
|
||||
- description: DU_DOTCLKIN3 input clock
|
||||
|
||||
clock-names:
|
||||
minItems: 3
|
||||
maxItems: 6
|
||||
items:
|
||||
- const: du.0
|
||||
- const: du.1
|
||||
- const: du.3
|
||||
- pattern: '^dclkin\.[013]$'
|
||||
- pattern: '^dclkin\.[013]$'
|
||||
- pattern: '^dclkin\.[013]$'
|
||||
|
||||
interrupts:
|
||||
maxItems: 3
|
||||
|
||||
resets:
|
||||
maxItems: 2
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: du.0
|
||||
- const: du.3
|
||||
|
||||
ports:
|
||||
properties:
|
||||
port@0:
|
||||
description: DPAD 0
|
||||
port@1:
|
||||
description: HDMI 0
|
||||
port@2:
|
||||
description: LVDS 0
|
||||
port@3: false
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
- port@2
|
||||
|
||||
renesas,cmms:
|
||||
minItems: 3
|
||||
|
||||
renesas,vsps:
|
||||
minItems: 3
|
||||
|
||||
required:
|
||||
- clock-names
|
||||
- interrupts
|
||||
- resets
|
||||
- reset-names
|
||||
- renesas,vsps
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,du-r8a77970
|
||||
- renesas,du-r8a77980
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- description: Functional clock for DU0
|
||||
- description: DU_DOTCLKIN0 input clock
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- const: du.0
|
||||
- const: dclkin.0
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: du.0
|
||||
|
||||
ports:
|
||||
properties:
|
||||
port@0:
|
||||
description: DPAD 0
|
||||
port@1:
|
||||
description: LVDS 0
|
||||
port@2: false
|
||||
port@3: false
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
renesas,vsps:
|
||||
minItems: 1
|
||||
|
||||
required:
|
||||
- clock-names
|
||||
- interrupts
|
||||
- resets
|
||||
- reset-names
|
||||
- renesas,vsps
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,du-r8a774c0
|
||||
- renesas,du-r8a77990
|
||||
- renesas,du-r8a77995
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
items:
|
||||
- description: Functional clock for DU0
|
||||
- description: Functional clock for DU1
|
||||
- description: DU_DOTCLKIN0 input clock
|
||||
- description: DU_DOTCLKIN1 input clock
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
items:
|
||||
- const: du.0
|
||||
- const: du.1
|
||||
- pattern: '^dclkin\.[01]$'
|
||||
- pattern: '^dclkin\.[01]$'
|
||||
|
||||
interrupts:
|
||||
maxItems: 2
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: du.0
|
||||
|
||||
ports:
|
||||
properties:
|
||||
port@0:
|
||||
description: DPAD 0
|
||||
port@1:
|
||||
description: LVDS 0
|
||||
port@2:
|
||||
description: LVDS 1
|
||||
# port@3 is TCON, not supported yet
|
||||
port@3: false
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
- port@2
|
||||
|
||||
renesas,cmms:
|
||||
minItems: 2
|
||||
|
||||
renesas,vsps:
|
||||
minItems: 2
|
||||
|
||||
required:
|
||||
- clock-names
|
||||
- interrupts
|
||||
- resets
|
||||
- reset-names
|
||||
- renesas,vsps
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# R-Car H3 ES2.0 DU
|
||||
- |
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
display@feb00000 {
|
||||
compatible = "renesas,du-r8a7795";
|
||||
reg = <0xfeb00000 0x80000>;
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 721>;
|
||||
clock-names = "du.0", "du.1", "du.2", "du.3";
|
||||
resets = <&cpg 724>, <&cpg 722>;
|
||||
reset-names = "du.0", "du.2";
|
||||
|
||||
renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>;
|
||||
renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7123_in>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dw_hdmi0_in>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dw_hdmi1_in>;
|
||||
};
|
||||
};
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
endpoint {
|
||||
remote-endpoint = <&lvds0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -1,74 +0,0 @@
|
||||
Rockchip DWC HDMI TX Encoder
|
||||
============================
|
||||
|
||||
The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
|
||||
with a companion PHY IP.
|
||||
|
||||
These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
|
||||
Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
|
||||
following device-specific properties.
|
||||
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be one of the following:
|
||||
"rockchip,rk3228-dw-hdmi"
|
||||
"rockchip,rk3288-dw-hdmi"
|
||||
"rockchip,rk3328-dw-hdmi"
|
||||
"rockchip,rk3399-dw-hdmi"
|
||||
- reg: See dw_hdmi.txt.
|
||||
- reg-io-width: See dw_hdmi.txt. Shall be 4.
|
||||
- interrupts: HDMI interrupt number
|
||||
- clocks: See dw_hdmi.txt.
|
||||
- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
|
||||
- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
|
||||
corresponding to the video input of the controller. The port shall have two
|
||||
endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
|
||||
- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
|
||||
|
||||
Optional properties
|
||||
|
||||
- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
|
||||
or the functionally-reduced I2C master contained in the DWC HDMI. When
|
||||
connected to a system I2C master this property contains a phandle to that
|
||||
I2C master controller.
|
||||
- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
|
||||
- clock-names: May contain "cec" as defined in dw_hdmi.txt.
|
||||
- clock-names: May contain "grf", power for grf io.
|
||||
- clock-names: May contain "vpll", external clock for some hdmi phy.
|
||||
- phys: from general PHY binding: the phandle for the PHY device.
|
||||
- phy-names: Should be "hdmi" if phys references an external phy.
|
||||
|
||||
Optional pinctrl entry:
|
||||
- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
|
||||
will switch to the unwedge pinctrl state for 10ms if it ever gets an
|
||||
i2c timeout. It's intended that this unwedge pinctrl entry will
|
||||
cause the SDA line to be driven low to work around a hardware
|
||||
errata.
|
||||
|
||||
Example:
|
||||
|
||||
hdmi: hdmi@ff980000 {
|
||||
compatible = "rockchip,rk3288-dw-hdmi";
|
||||
reg = <0xff980000 0x20000>;
|
||||
reg-io-width = <4>;
|
||||
ddc-i2c-bus = <&i2c5>;
|
||||
rockchip,grf = <&grf>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
|
||||
clock-names = "iahb", "isfr";
|
||||
ports {
|
||||
hdmi_in: port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
hdmi_in_vopb: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&vopb_out_hdmi>;
|
||||
};
|
||||
hdmi_in_vopl: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&vopl_out_hdmi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,156 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip DWC HDMI TX Encoder
|
||||
|
||||
maintainers:
|
||||
- Mark Yao <markyao0591@gmail.com>
|
||||
|
||||
description: |
|
||||
The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
|
||||
with a companion PHY IP.
|
||||
|
||||
allOf:
|
||||
- $ref: ../bridge/synopsys,dw-hdmi.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3228-dw-hdmi
|
||||
- rockchip,rk3288-dw-hdmi
|
||||
- rockchip,rk3328-dw-hdmi
|
||||
- rockchip,rk3399-dw-hdmi
|
||||
|
||||
reg-io-width:
|
||||
const: 4
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 5
|
||||
items:
|
||||
- {}
|
||||
- {}
|
||||
# The next three clocks are all optional, but shall be specified in this
|
||||
# order when present.
|
||||
- description: The HDMI CEC controller main clock
|
||||
- description: Power for GRF IO
|
||||
- description: External clock for some HDMI PHY
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
maxItems: 5
|
||||
items:
|
||||
- {}
|
||||
- {}
|
||||
- enum:
|
||||
- cec
|
||||
- grf
|
||||
- vpll
|
||||
- enum:
|
||||
- grf
|
||||
- vpll
|
||||
- const: vpll
|
||||
|
||||
ddc-i2c-bus:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
The HDMI DDC bus can be connected to either a system I2C master or the
|
||||
functionally-reduced I2C master contained in the DWC HDMI. When connected
|
||||
to a system I2C master this property contains a phandle to that I2C
|
||||
master controller.
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
description: The HDMI PHY
|
||||
|
||||
phy-names:
|
||||
const: hdmi
|
||||
|
||||
pinctrl-names:
|
||||
description:
|
||||
The unwedge pinctrl entry shall drive the DDC SDA line low. This is
|
||||
intended to work around a hardware errata that can cause the DDC I2C
|
||||
bus to be wedged.
|
||||
items:
|
||||
- const: default
|
||||
- const: unwedge
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port:
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: Input of the DWC HDMI TX
|
||||
|
||||
properties:
|
||||
endpoint@0:
|
||||
$ref: /schemas/graph.yaml#/properties/endpoint
|
||||
description: Connection to the VOPB
|
||||
|
||||
endpoint@1:
|
||||
$ref: /schemas/graph.yaml#/properties/endpoint
|
||||
description: Connection to the VOPL
|
||||
|
||||
required:
|
||||
- endpoint@0
|
||||
- endpoint@1
|
||||
|
||||
required:
|
||||
- port
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
phandle to the GRF to mux vopl/vopb.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-io-width
|
||||
- clocks
|
||||
- clock-names
|
||||
- interrupts
|
||||
- ports
|
||||
- rockchip,grf
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/rk3288-cru.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
hdmi: hdmi@ff980000 {
|
||||
compatible = "rockchip,rk3288-dw-hdmi";
|
||||
reg = <0xff980000 0x20000>;
|
||||
reg-io-width = <4>;
|
||||
ddc-i2c-bus = <&i2c5>;
|
||||
rockchip,grf = <&grf>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
|
||||
clock-names = "iahb", "isfr";
|
||||
|
||||
ports {
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hdmi_in_vopb: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&vopb_out_hdmi>;
|
||||
};
|
||||
hdmi_in_vopl: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&vopl_out_hdmi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -23,6 +23,7 @@ properties:
|
||||
- enum:
|
||||
- ingenic,jz4775-intc
|
||||
- ingenic,jz4770-intc
|
||||
- ingenic,jz4760b-intc
|
||||
- const: ingenic,jz4760-intc
|
||||
- items:
|
||||
- const: ingenic,x1000-intc
|
||||
|
||||
@ -257,3 +257,79 @@ fences in the kernel. This means:
|
||||
userspace is allowed to use userspace fencing or long running compute
|
||||
workloads. This also means no implicit fencing for shared buffers in these
|
||||
cases.
|
||||
|
||||
Recoverable Hardware Page Faults Implications
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Modern hardware supports recoverable page faults, which has a lot of
|
||||
implications for DMA fences.
|
||||
|
||||
First, a pending page fault obviously holds up the work that's running on the
|
||||
accelerator and a memory allocation is usually required to resolve the fault.
|
||||
But memory allocations are not allowed to gate completion of DMA fences, which
|
||||
means any workload using recoverable page faults cannot use DMA fences for
|
||||
synchronization. Synchronization fences controlled by userspace must be used
|
||||
instead.
|
||||
|
||||
On GPUs this poses a problem, because current desktop compositor protocols on
|
||||
Linux rely on DMA fences, which means without an entirely new userspace stack
|
||||
built on top of userspace fences, they cannot benefit from recoverable page
|
||||
faults. Specifically this means implicit synchronization will not be possible.
|
||||
The exception is when page faults are only used as migration hints and never to
|
||||
on-demand fill a memory request. For now this means recoverable page
|
||||
faults on GPUs are limited to pure compute workloads.
|
||||
|
||||
Furthermore GPUs usually have shared resources between the 3D rendering and
|
||||
compute side, like compute units or command submission engines. If both a 3D
|
||||
job with a DMA fence and a compute workload using recoverable page faults are
|
||||
pending they could deadlock:
|
||||
|
||||
- The 3D workload might need to wait for the compute job to finish and release
|
||||
hardware resources first.
|
||||
|
||||
- The compute workload might be stuck in a page fault, because the memory
|
||||
allocation is waiting for the DMA fence of the 3D workload to complete.
|
||||
|
||||
There are a few options to prevent this problem, one of which drivers need to
|
||||
ensure:
|
||||
|
||||
- Compute workloads can always be preempted, even when a page fault is pending
|
||||
and not yet repaired. Not all hardware supports this.
|
||||
|
||||
- DMA fence workloads and workloads which need page fault handling have
|
||||
independent hardware resources to guarantee forward progress. This could be
|
||||
achieved through e.g. through dedicated engines and minimal compute unit
|
||||
reservations for DMA fence workloads.
|
||||
|
||||
- The reservation approach could be further refined by only reserving the
|
||||
hardware resources for DMA fence workloads when they are in-flight. This must
|
||||
cover the time from when the DMA fence is visible to other threads up to
|
||||
moment when fence is completed through dma_fence_signal().
|
||||
|
||||
- As a last resort, if the hardware provides no useful reservation mechanics,
|
||||
all workloads must be flushed from the GPU when switching between jobs
|
||||
requiring DMA fences or jobs requiring page fault handling: This means all DMA
|
||||
fences must complete before a compute job with page fault handling can be
|
||||
inserted into the scheduler queue. And vice versa, before a DMA fence can be
|
||||
made visible anywhere in the system, all compute workloads must be preempted
|
||||
to guarantee all pending GPU page faults are flushed.
|
||||
|
||||
- Only a fairly theoretical option would be to untangle these dependencies when
|
||||
allocating memory to repair hardware page faults, either through separate
|
||||
memory blocks or runtime tracking of the full dependency graph of all DMA
|
||||
fences. This results very wide impact on the kernel, since resolving the page
|
||||
on the CPU side can itself involve a page fault. It is much more feasible and
|
||||
robust to limit the impact of handling hardware page faults to the specific
|
||||
driver.
|
||||
|
||||
Note that workloads that run on independent hardware like copy engines or other
|
||||
GPUs do not have any impact. This allows us to keep using DMA fences internally
|
||||
in the kernel even for resolving hardware page faults, e.g. by using copy
|
||||
engines to clear or copy memory needed to resolve the page fault.
|
||||
|
||||
In some ways this page fault problem is a special case of the `Infinite DMA
|
||||
Fences` discussions: Infinite fences from compute workloads are allowed to
|
||||
depend on DMA fences, but not the other way around. And not even the page fault
|
||||
problem is new, because some other CPU thread in userspace might
|
||||
hit a page fault which holds up a userspace fence - supporting page faults on
|
||||
GPUs doesn't anything fundamentally new.
|
||||
|
||||
@ -80,6 +80,18 @@ Atomic State Helper Reference
|
||||
.. kernel-doc:: drivers/gpu/drm/drm_atomic_state_helper.c
|
||||
:export:
|
||||
|
||||
GEM Atomic Helper Reference
|
||||
---------------------------
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/drm_gem_atomic_helper.c
|
||||
:doc: overview
|
||||
|
||||
.. kernel-doc:: include/drm/drm_gem_atomic_helper.h
|
||||
:internal:
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/drm_gem_atomic_helper.c
|
||||
:export:
|
||||
|
||||
Simple KMS Helper Reference
|
||||
===========================
|
||||
|
||||
|
||||
@ -16,6 +16,7 @@ Linux GPU Driver Developer's Guide
|
||||
vga-switcheroo
|
||||
vgaarbiter
|
||||
todo
|
||||
rfc/index
|
||||
|
||||
.. only:: subproject and html
|
||||
|
||||
|
||||
17
Documentation/gpu/rfc/index.rst
Normal file
17
Documentation/gpu/rfc/index.rst
Normal file
@ -0,0 +1,17 @@
|
||||
===============
|
||||
GPU RFC Section
|
||||
===============
|
||||
|
||||
For complex work, especially new uapi, it is often good to nail the high level
|
||||
design issues before getting lost in the code details. This section is meant to
|
||||
host such documentation:
|
||||
|
||||
* Each RFC should be a section in this file, explaining the goal and main design
|
||||
considerations. Especially for uapi make sure you Cc: all relevant project
|
||||
mailing lists and involved people outside of dri-devel.
|
||||
|
||||
* For uapi structures add a file to this directory with and then pull the
|
||||
kerneldoc in like with real uapi headers.
|
||||
|
||||
* Once the code has landed move all the documentation to the right places in
|
||||
the main core, helper or driver sections.
|
||||
@ -459,52 +459,6 @@ Contact: Emil Velikov, respective driver maintainers
|
||||
|
||||
Level: Intermediate
|
||||
|
||||
Plumb drm_atomic_state all over
|
||||
-------------------------------
|
||||
|
||||
Currently various atomic functions take just a single or a handful of
|
||||
object states (eg. plane state). While that single object state can
|
||||
suffice for some simple cases, we often have to dig out additional
|
||||
object states for dealing with various dependencies between the individual
|
||||
objects or the hardware they represent. The process of digging out the
|
||||
additional states is rather non-intuitive and error prone.
|
||||
|
||||
To fix that most functions should rather take the overall
|
||||
drm_atomic_state as one of their parameters. The other parameters
|
||||
would generally be the object(s) we mainly want to interact with.
|
||||
|
||||
For example, instead of
|
||||
|
||||
.. code-block:: c
|
||||
|
||||
int (*atomic_check)(struct drm_plane *plane, struct drm_plane_state *state);
|
||||
|
||||
we would have something like
|
||||
|
||||
.. code-block:: c
|
||||
|
||||
int (*atomic_check)(struct drm_plane *plane, struct drm_atomic_state *state);
|
||||
|
||||
The implementation can then trivially gain access to any required object
|
||||
state(s) via drm_atomic_get_plane_state(), drm_atomic_get_new_plane_state(),
|
||||
drm_atomic_get_old_plane_state(), and their equivalents for
|
||||
other object types.
|
||||
|
||||
Additionally many drivers currently access the object->state pointer
|
||||
directly in their commit functions. That is not going to work if we
|
||||
eg. want to allow deeper commit pipelines as those pointers could
|
||||
then point to the states corresponding to a future commit instead of
|
||||
the current commit we're trying to process. Also non-blocking commits
|
||||
execute locklessly so there are serious concerns with dereferencing
|
||||
the object->state pointers without holding the locks that protect them.
|
||||
Use of drm_atomic_get_new_plane_state(), drm_atomic_get_old_plane_state(),
|
||||
etc. avoids these problems as well since they relate to a specific
|
||||
commit via the passed in drm_atomic_state.
|
||||
|
||||
Contact: Ville Syrjälä, Daniel Vetter
|
||||
|
||||
Level: Intermediate
|
||||
|
||||
Use struct dma_buf_map throughout codebase
|
||||
------------------------------------------
|
||||
|
||||
@ -596,23 +550,48 @@ Contact: Daniel Vetter
|
||||
|
||||
Level: Intermediate
|
||||
|
||||
KMS cleanups
|
||||
------------
|
||||
Object lifetime fixes
|
||||
---------------------
|
||||
|
||||
Some of these date from the very introduction of KMS in 2008 ...
|
||||
There's two related issues here
|
||||
|
||||
- Make ->funcs and ->helper_private vtables optional. There's a bunch of empty
|
||||
function tables in drivers, but before we can remove them we need to make sure
|
||||
that all the users in helpers and drivers do correctly check for a NULL
|
||||
vtable.
|
||||
- Cleanup up the various ->destroy callbacks, which often are all the same
|
||||
simple code.
|
||||
|
||||
- Cleanup up the various ->destroy callbacks. A lot of them just wrapt the
|
||||
drm_*_cleanup implementations and can be removed. Some tack a kfree() at the
|
||||
end, for which we could add drm_*_cleanup_kfree(). And then there's the (for
|
||||
historical reasons) misnamed drm_primary_helper_destroy() function.
|
||||
- Lots of drivers erroneously allocate DRM modeset objects using devm_kzalloc,
|
||||
which results in use-after free issues on driver unload. This can be serious
|
||||
trouble even for drivers for hardware integrated on the SoC due to
|
||||
EPROBE_DEFERRED backoff.
|
||||
|
||||
Both these problems can be solved by switching over to drmm_kzalloc(), and the
|
||||
various convenience wrappers provided, e.g. drmm_crtc_alloc_with_planes(),
|
||||
drmm_universal_plane_alloc(), ... and so on.
|
||||
|
||||
Contact: Daniel Vetter
|
||||
|
||||
Level: Intermediate
|
||||
|
||||
Remove automatic page mapping from dma-buf importing
|
||||
----------------------------------------------------
|
||||
|
||||
When importing dma-bufs, the dma-buf and PRIME frameworks automatically map
|
||||
imported pages into the importer's DMA area. drm_gem_prime_fd_to_handle() and
|
||||
drm_gem_prime_handle_to_fd() require that importers call dma_buf_attach()
|
||||
even if they never do actual device DMA, but only CPU access through
|
||||
dma_buf_vmap(). This is a problem for USB devices, which do not support DMA
|
||||
operations.
|
||||
|
||||
To fix the issue, automatic page mappings should be removed from the
|
||||
buffer-sharing code. Fixing this is a bit more involved, since the import/export
|
||||
cache is also tied to &drm_gem_object.import_attach. Meanwhile we paper over
|
||||
this problem for USB devices by fishing out the USB host controller device, as
|
||||
long as that supports DMA. Otherwise importing can still needlessly fail.
|
||||
|
||||
Contact: Thomas Zimmermann <tzimmermann@suse.de>, Daniel Vetter
|
||||
|
||||
Level: Advanced
|
||||
|
||||
|
||||
Better Testing
|
||||
==============
|
||||
|
||||
@ -645,8 +624,6 @@ See the documentation of :ref:`VKMS <vkms>` for more details. This is an ideal
|
||||
internship task, since it only requires a virtual machine and can be sized to
|
||||
fit the available time.
|
||||
|
||||
Contact: Daniel Vetter
|
||||
|
||||
Level: See details
|
||||
|
||||
Backlight Refactoring
|
||||
@ -700,7 +677,7 @@ Outside DRM
|
||||
Convert fbdev drivers to DRM
|
||||
----------------------------
|
||||
|
||||
There are plenty of fbdev drivers for older hardware. Some hwardware has
|
||||
There are plenty of fbdev drivers for older hardware. Some hardware has
|
||||
become obsolete, but some still provides good(-enough) framebuffers. The
|
||||
drivers that are still useful should be converted to DRM and afterwards
|
||||
removed from fbdev.
|
||||
|
||||
@ -1988,7 +1988,7 @@ netif_carrier.
|
||||
If use_carrier is 0, then the MII monitor will first query the
|
||||
device's (via ioctl) MII registers and check the link state. If that
|
||||
request fails (not just that it returns carrier down), then the MII
|
||||
monitor will make an ethtool ETHOOL_GLINK request to attempt to obtain
|
||||
monitor will make an ethtool ETHTOOL_GLINK request to attempt to obtain
|
||||
the same information. If both methods fail (i.e., the driver either
|
||||
does not support or had some error in processing both the MII register
|
||||
and ethtool requests), then the MII monitor will assume the link is
|
||||
|
||||
@ -142,73 +142,13 @@ Please send incremental versions on top of what has been merged in order to fix
|
||||
the patches the way they would look like if your latest patch series was to be
|
||||
merged.
|
||||
|
||||
How can I tell what patches are queued up for backporting to the various stable releases?
|
||||
-----------------------------------------------------------------------------------------
|
||||
Normally Greg Kroah-Hartman collects stable commits himself, but for
|
||||
networking, Dave collects up patches he deems critical for the
|
||||
networking subsystem, and then hands them off to Greg.
|
||||
|
||||
There is a patchworks queue that you can see here:
|
||||
|
||||
https://patchwork.kernel.org/bundle/netdev/stable/?state=*
|
||||
|
||||
It contains the patches which Dave has selected, but not yet handed off
|
||||
to Greg. If Greg already has the patch, then it will be here:
|
||||
|
||||
https://git.kernel.org/pub/scm/linux/kernel/git/stable/stable-queue.git
|
||||
|
||||
A quick way to find whether the patch is in this stable-queue is to
|
||||
simply clone the repo, and then git grep the mainline commit ID, e.g.
|
||||
::
|
||||
|
||||
stable-queue$ git grep -l 284041ef21fdf2e
|
||||
releases/3.0.84/ipv6-fix-possible-crashes-in-ip6_cork_release.patch
|
||||
releases/3.4.51/ipv6-fix-possible-crashes-in-ip6_cork_release.patch
|
||||
releases/3.9.8/ipv6-fix-possible-crashes-in-ip6_cork_release.patch
|
||||
stable/stable-queue$
|
||||
|
||||
I see a network patch and I think it should be backported to stable. Should I request it via stable@vger.kernel.org like the references in the kernel's Documentation/process/stable-kernel-rules.rst file say?
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
No, not for networking. Check the stable queues as per above first
|
||||
to see if it is already queued. If not, then send a mail to netdev,
|
||||
listing the upstream commit ID and why you think it should be a stable
|
||||
candidate.
|
||||
|
||||
Before you jump to go do the above, do note that the normal stable rules
|
||||
in :ref:`Documentation/process/stable-kernel-rules.rst <stable_kernel_rules>`
|
||||
still apply. So you need to explicitly indicate why it is a critical
|
||||
fix and exactly what users are impacted. In addition, you need to
|
||||
convince yourself that you *really* think it has been overlooked,
|
||||
vs. having been considered and rejected.
|
||||
|
||||
Generally speaking, the longer it has had a chance to "soak" in
|
||||
mainline, the better the odds that it is an OK candidate for stable. So
|
||||
scrambling to request a commit be added the day after it appears should
|
||||
be avoided.
|
||||
|
||||
I have created a network patch and I think it should be backported to stable. Should I add a Cc: stable@vger.kernel.org like the references in the kernel's Documentation/ directory say?
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
No. See above answer. In short, if you think it really belongs in
|
||||
stable, then ensure you write a decent commit log that describes who
|
||||
gets impacted by the bug fix and how it manifests itself, and when the
|
||||
bug was introduced. If you do that properly, then the commit will get
|
||||
handled appropriately and most likely get put in the patchworks stable
|
||||
queue if it really warrants it.
|
||||
|
||||
If you think there is some valid information relating to it being in
|
||||
stable that does *not* belong in the commit log, then use the three dash
|
||||
marker line as described in
|
||||
:ref:`Documentation/process/submitting-patches.rst <the_canonical_patch_format>`
|
||||
to temporarily embed that information into the patch that you send.
|
||||
|
||||
Are all networking bug fixes backported to all stable releases?
|
||||
Are there special rules regarding stable submissions on netdev?
|
||||
---------------------------------------------------------------
|
||||
Due to capacity, Dave could only take care of the backports for the
|
||||
last two stable releases. For earlier stable releases, each stable
|
||||
branch maintainer is supposed to take care of them. If you find any
|
||||
patch is missing from an earlier stable branch, please notify
|
||||
stable@vger.kernel.org with either a commit ID or a formal patch
|
||||
backported, and CC Dave and other relevant networking developers.
|
||||
While it used to be the case that netdev submissions were not supposed
|
||||
to carry explicit ``CC: stable@vger.kernel.org`` tags that is no longer
|
||||
the case today. Please follow the standard stable rules in
|
||||
:ref:`Documentation/process/stable-kernel-rules.rst <stable_kernel_rules>`,
|
||||
and make sure you include appropriate Fixes tags!
|
||||
|
||||
Is the comment style convention different for the networking content?
|
||||
---------------------------------------------------------------------
|
||||
|
||||
@ -35,12 +35,6 @@ Rules on what kind of patches are accepted, and which ones are not, into the
|
||||
Procedure for submitting patches to the -stable tree
|
||||
----------------------------------------------------
|
||||
|
||||
- If the patch covers files in net/ or drivers/net please follow netdev stable
|
||||
submission guidelines as described in
|
||||
:ref:`Documentation/networking/netdev-FAQ.rst <netdev-FAQ>`
|
||||
after first checking the stable networking queue at
|
||||
https://patchwork.kernel.org/bundle/netdev/stable/?state=*
|
||||
to ensure the requested patch is not already queued up.
|
||||
- Security patches should not be handled (solely) by the -stable review
|
||||
process but should follow the procedures in
|
||||
:ref:`Documentation/admin-guide/security-bugs.rst <securitybugs>`.
|
||||
|
||||
@ -250,11 +250,6 @@ should also read
|
||||
:ref:`Documentation/process/stable-kernel-rules.rst <stable_kernel_rules>`
|
||||
in addition to this file.
|
||||
|
||||
Note, however, that some subsystem maintainers want to come to their own
|
||||
conclusions on which patches should go to the stable trees. The networking
|
||||
maintainer, in particular, would rather not see individual developers
|
||||
adding lines like the above to their patches.
|
||||
|
||||
If changes affect userland-kernel interfaces, please send the MAN-PAGES
|
||||
maintainer (as listed in the MAINTAINERS file) a man-pages patch, or at
|
||||
least a notification of the change, so that some information makes its way
|
||||
|
||||
@ -182,6 +182,9 @@ is dependent on the CPU capability and the kernel configuration. The limit can
|
||||
be retrieved using KVM_CAP_ARM_VM_IPA_SIZE of the KVM_CHECK_EXTENSION
|
||||
ioctl() at run-time.
|
||||
|
||||
Creation of the VM will fail if the requested IPA size (whether it is
|
||||
implicit or explicit) is unsupported on the host.
|
||||
|
||||
Please note that configuring the IPA size does not affect the capability
|
||||
exposed by the guest CPUs in ID_AA64MMFR0_EL1[PARange]. It only affects
|
||||
size of the address translated by the stage2 level (guest physical to
|
||||
|
||||
41
MAINTAINERS
41
MAINTAINERS
@ -261,8 +261,8 @@ ABI/API
|
||||
L: linux-api@vger.kernel.org
|
||||
F: include/linux/syscalls.h
|
||||
F: kernel/sys_ni.c
|
||||
F: include/uapi/
|
||||
F: arch/*/include/uapi/
|
||||
X: include/uapi/
|
||||
X: arch/*/include/uapi/
|
||||
|
||||
ABIT UGURU 1,2 HARDWARE MONITOR DRIVER
|
||||
M: Hans de Goede <hdegoede@redhat.com>
|
||||
@ -1323,7 +1323,7 @@ ARC PGU DRM DRIVER
|
||||
M: Alexey Brodkin <abrodkin@synopsys.com>
|
||||
S: Supported
|
||||
F: Documentation/devicetree/bindings/display/snps,arcpgu.txt
|
||||
F: drivers/gpu/drm/arc/
|
||||
F: drivers/gpu/drm/tiny/arcpgu.c
|
||||
|
||||
ARCNET NETWORK LAYER
|
||||
M: Michael Grzeschik <m.grzeschik@pengutronix.de>
|
||||
@ -5568,6 +5568,12 @@ S: Maintained
|
||||
F: Documentation/devicetree/bindings/display/panel/boe,himax8279d.yaml
|
||||
F: drivers/gpu/drm/panel/panel-boe-himax8279d.c
|
||||
|
||||
DRM DRIVER FOR CHIPONE ICN6211 MIPI-DSI to RGB CONVERTER BRIDGE
|
||||
M: Jagan Teki <jagan@amarulasolutions.com>
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml
|
||||
F: drivers/gpu/drm/bridge/chipone-icn6211.c
|
||||
|
||||
DRM DRIVER FOR FARADAY TVE200 TV ENCODER
|
||||
M: Linus Walleij <linus.walleij@linaro.org>
|
||||
S: Maintained
|
||||
@ -5586,6 +5592,14 @@ S: Maintained
|
||||
F: Documentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.yaml
|
||||
F: drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
|
||||
|
||||
DRM DRIVER FOR GENERIC USB DISPLAY
|
||||
M: Noralf Trønnes <noralf@tronnes.org>
|
||||
S: Maintained
|
||||
W: https://github.com/notro/gud/wiki
|
||||
T: git git://anongit.freedesktop.org/drm/drm-misc
|
||||
F: drivers/gpu/drm/gud/
|
||||
F: include/drm/gud.h
|
||||
|
||||
DRM DRIVER FOR GRAIN MEDIA GM12U320 PROJECTORS
|
||||
M: Hans de Goede <hdegoede@redhat.com>
|
||||
S: Maintained
|
||||
@ -5835,7 +5849,7 @@ M: David Airlie <airlied@linux.ie>
|
||||
M: Daniel Vetter <daniel@ffwll.ch>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Maintained
|
||||
B: https://bugs.freedesktop.org/
|
||||
B: https://gitlab.freedesktop.org/drm
|
||||
C: irc://chat.freenode.net/dri-devel
|
||||
T: git git://anongit.freedesktop.org/drm/drm
|
||||
F: Documentation/devicetree/bindings/display/
|
||||
@ -5894,6 +5908,7 @@ F: drivers/gpu/drm/atmel-hlcdc/
|
||||
DRM DRIVERS FOR BRIDGE CHIPS
|
||||
M: Andrzej Hajda <a.hajda@samsung.com>
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
|
||||
M: Robert Foss <robert.foss@linaro.org>
|
||||
R: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
|
||||
R: Jonas Karlman <jonas@kwiboo.se>
|
||||
R: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
@ -5963,6 +5978,7 @@ DRM DRIVERS FOR MEDIATEK
|
||||
M: Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
M: Philipp Zabel <p.zabel@pengutronix.de>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Supported
|
||||
F: Documentation/devicetree/bindings/display/mediatek/
|
||||
F: drivers/gpu/drm/mediatek/
|
||||
@ -5988,9 +6004,9 @@ L: dri-devel@lists.freedesktop.org
|
||||
L: linux-renesas-soc@vger.kernel.org
|
||||
S: Supported
|
||||
T: git git://linuxtv.org/pinchartl/media drm/du/next
|
||||
F: Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
|
||||
F: Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
|
||||
F: Documentation/devicetree/bindings/display/bridge/renesas,lvds.yaml
|
||||
F: Documentation/devicetree/bindings/display/renesas,du.txt
|
||||
F: Documentation/devicetree/bindings/display/renesas,du.yaml
|
||||
F: drivers/gpu/drm/rcar-du/
|
||||
F: drivers/gpu/drm/shmobile/
|
||||
F: include/linux/platform_data/shmob_drm.h
|
||||
@ -10460,6 +10476,12 @@ S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git
|
||||
F: drivers/hid/hid-lg-g15.c
|
||||
|
||||
LONTIUM LT8912B MIPI TO HDMI BRIDGE
|
||||
M: Adrien Grassein <adrien.grassein@gmail.com>
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/display/bridge/lontium,lt8912b.yaml
|
||||
F: drivers/gpu/drm/bridge/lontium-lt8912b.c
|
||||
|
||||
LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI)
|
||||
M: Sathya Prakash <sathya.prakash@broadcom.com>
|
||||
M: Sreekanth Reddy <sreekanth.reddy@broadcom.com>
|
||||
@ -10716,7 +10738,8 @@ F: drivers/net/ethernet/marvell/mvpp2/
|
||||
|
||||
MARVELL MWIFIEX WIRELESS DRIVER
|
||||
M: Amitkumar Karwar <amitkarwar@gmail.com>
|
||||
M: Ganapathi Bhat <ganapathi.bhat@nxp.com>
|
||||
M: Ganapathi Bhat <ganapathi017@gmail.com>
|
||||
M: Sharvari Harisangam <sharvari.harisangam@nxp.com>
|
||||
M: Xinming Hu <huxinming820@gmail.com>
|
||||
L: linux-wireless@vger.kernel.org
|
||||
S: Maintained
|
||||
@ -12266,7 +12289,7 @@ M: Stefan Agner <stefan@agner.ch>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Supported
|
||||
T: git git://anongit.freedesktop.org/drm/drm-misc
|
||||
F: Documentation/devicetree/bindings/display/mxsfb.txt
|
||||
F: Documentation/devicetree/bindings/display/fsl,lcdif.yaml
|
||||
F: drivers/gpu/drm/mxsfb/
|
||||
|
||||
MYLEX DAC960 PCI RAID Controller
|
||||
@ -19165,7 +19188,7 @@ S: Maintained
|
||||
F: drivers/infiniband/hw/vmw_pvrdma/
|
||||
|
||||
VMware PVSCSI driver
|
||||
M: Jim Gill <jgill@vmware.com>
|
||||
M: Vishal Bhakta <vbhakta@vmware.com>
|
||||
M: VMware PV-Drivers <pv-drivers@vmware.com>
|
||||
L: linux-scsi@vger.kernel.org
|
||||
S: Maintained
|
||||
|
||||
6
Makefile
6
Makefile
@ -2,7 +2,7 @@
|
||||
VERSION = 5
|
||||
PATCHLEVEL = 12
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc2
|
||||
EXTRAVERSION = -rc3
|
||||
NAME = Frozen Wasteland
|
||||
|
||||
# *DOCUMENTATION*
|
||||
@ -264,7 +264,8 @@ no-dot-config-targets := $(clean-targets) \
|
||||
$(version_h) headers headers_% archheaders archscripts \
|
||||
%asm-generic kernelversion %src-pkg dt_binding_check \
|
||||
outputmakefile
|
||||
no-sync-config-targets := $(no-dot-config-targets) %install kernelrelease
|
||||
no-sync-config-targets := $(no-dot-config-targets) %install kernelrelease \
|
||||
image_name
|
||||
single-targets := %.a %.i %.ko %.lds %.ll %.lst %.mod %.o %.s %.symtypes %/
|
||||
|
||||
config-build :=
|
||||
@ -478,6 +479,7 @@ USERINCLUDE := \
|
||||
-I$(objtree)/arch/$(SRCARCH)/include/generated/uapi \
|
||||
-I$(srctree)/include/uapi \
|
||||
-I$(objtree)/include/generated/uapi \
|
||||
-include $(srctree)/include/linux/compiler-version.h \
|
||||
-include $(srctree)/include/linux/kconfig.h
|
||||
|
||||
# Use LINUXINCLUDE when you must reference the include/ directory.
|
||||
|
||||
@ -632,13 +632,12 @@ config HAS_LTO_CLANG
|
||||
def_bool y
|
||||
# Clang >= 11: https://github.com/ClangBuiltLinux/linux/issues/510
|
||||
depends on CC_IS_CLANG && CLANG_VERSION >= 110000 && LD_IS_LLD
|
||||
depends on $(success,test $(LLVM) -eq 1)
|
||||
depends on $(success,test $(LLVM_IAS) -eq 1)
|
||||
depends on $(success,$(NM) --help | head -n 1 | grep -qi llvm)
|
||||
depends on $(success,$(AR) --help | head -n 1 | grep -qi llvm)
|
||||
depends on ARCH_SUPPORTS_LTO_CLANG
|
||||
depends on !FTRACE_MCOUNT_USE_RECORDMCOUNT
|
||||
depends on !KASAN
|
||||
depends on !KASAN || KASAN_HW_TAGS
|
||||
depends on !GCOV_KERNEL
|
||||
help
|
||||
The compiler and Kconfig options support building with Clang's
|
||||
|
||||
@ -348,6 +348,7 @@ config ARCH_EP93XX
|
||||
select ARM_AMBA
|
||||
imply ARM_PATCH_PHYS_VIRT
|
||||
select ARM_VIC
|
||||
select GENERIC_IRQ_MULTI_HANDLER
|
||||
select AUTO_ZRELADDR
|
||||
select CLKDEV_LOOKUP
|
||||
select CLKSRC_MMIO
|
||||
|
||||
@ -11,6 +11,7 @@
|
||||
|
||||
#include <xen/xen.h>
|
||||
#include <xen/interface/memory.h>
|
||||
#include <xen/grant_table.h>
|
||||
#include <xen/page.h>
|
||||
#include <xen/swiotlb-xen.h>
|
||||
|
||||
@ -109,7 +110,7 @@ int set_foreign_p2m_mapping(struct gnttab_map_grant_ref *map_ops,
|
||||
map_ops[i].status = GNTST_general_error;
|
||||
unmap.host_addr = map_ops[i].host_addr,
|
||||
unmap.handle = map_ops[i].handle;
|
||||
map_ops[i].handle = ~0;
|
||||
map_ops[i].handle = INVALID_GRANT_HANDLE;
|
||||
if (map_ops[i].flags & GNTMAP_device_map)
|
||||
unmap.dev_bus_addr = map_ops[i].dev_bus_addr;
|
||||
else
|
||||
@ -130,7 +131,6 @@ int set_foreign_p2m_mapping(struct gnttab_map_grant_ref *map_ops,
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(set_foreign_p2m_mapping);
|
||||
|
||||
int clear_foreign_p2m_mapping(struct gnttab_unmap_grant_ref *unmap_ops,
|
||||
struct gnttab_unmap_grant_ref *kunmap_ops,
|
||||
@ -145,7 +145,6 @@ int clear_foreign_p2m_mapping(struct gnttab_unmap_grant_ref *unmap_ops,
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clear_foreign_p2m_mapping);
|
||||
|
||||
bool __set_phys_to_machine_multi(unsigned long pfn,
|
||||
unsigned long mfn, unsigned long nr_pages)
|
||||
|
||||
@ -1055,8 +1055,6 @@ config HW_PERF_EVENTS
|
||||
config SYS_SUPPORTS_HUGETLBFS
|
||||
def_bool y
|
||||
|
||||
config ARCH_WANT_HUGE_PMD_SHARE
|
||||
|
||||
config ARCH_HAS_CACHE_LINE_SIZE
|
||||
def_bool y
|
||||
|
||||
@ -1157,8 +1155,8 @@ config XEN
|
||||
|
||||
config FORCE_MAX_ZONEORDER
|
||||
int
|
||||
default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
|
||||
default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
|
||||
default "14" if ARM64_64K_PAGES
|
||||
default "12" if ARM64_16K_PAGES
|
||||
default "11"
|
||||
help
|
||||
The kernel memory allocator divides physically contiguous memory
|
||||
@ -1855,12 +1853,6 @@ config CMDLINE_FROM_BOOTLOADER
|
||||
the boot loader doesn't provide any, the default kernel command
|
||||
string provided in CMDLINE will be used.
|
||||
|
||||
config CMDLINE_EXTEND
|
||||
bool "Extend bootloader kernel arguments"
|
||||
help
|
||||
The command-line arguments provided by the boot loader will be
|
||||
appended to the default kernel command string.
|
||||
|
||||
config CMDLINE_FORCE
|
||||
bool "Always use the default kernel command string"
|
||||
help
|
||||
|
||||
@ -47,10 +47,10 @@
|
||||
#define __KVM_HOST_SMCCC_FUNC___kvm_flush_vm_context 2
|
||||
#define __KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_vmid_ipa 3
|
||||
#define __KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_vmid 4
|
||||
#define __KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_local_vmid 5
|
||||
#define __KVM_HOST_SMCCC_FUNC___kvm_flush_cpu_context 5
|
||||
#define __KVM_HOST_SMCCC_FUNC___kvm_timer_set_cntvoff 6
|
||||
#define __KVM_HOST_SMCCC_FUNC___kvm_enable_ssbs 7
|
||||
#define __KVM_HOST_SMCCC_FUNC___vgic_v3_get_ich_vtr_el2 8
|
||||
#define __KVM_HOST_SMCCC_FUNC___vgic_v3_get_gic_config 8
|
||||
#define __KVM_HOST_SMCCC_FUNC___vgic_v3_read_vmcr 9
|
||||
#define __KVM_HOST_SMCCC_FUNC___vgic_v3_write_vmcr 10
|
||||
#define __KVM_HOST_SMCCC_FUNC___vgic_v3_init_lrs 11
|
||||
@ -183,16 +183,16 @@ DECLARE_KVM_HYP_SYM(__bp_harden_hyp_vecs);
|
||||
#define __bp_harden_hyp_vecs CHOOSE_HYP_SYM(__bp_harden_hyp_vecs)
|
||||
|
||||
extern void __kvm_flush_vm_context(void);
|
||||
extern void __kvm_flush_cpu_context(struct kvm_s2_mmu *mmu);
|
||||
extern void __kvm_tlb_flush_vmid_ipa(struct kvm_s2_mmu *mmu, phys_addr_t ipa,
|
||||
int level);
|
||||
extern void __kvm_tlb_flush_vmid(struct kvm_s2_mmu *mmu);
|
||||
extern void __kvm_tlb_flush_local_vmid(struct kvm_s2_mmu *mmu);
|
||||
|
||||
extern void __kvm_timer_set_cntvoff(u64 cntvoff);
|
||||
|
||||
extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
|
||||
|
||||
extern u64 __vgic_v3_get_ich_vtr_el2(void);
|
||||
extern u64 __vgic_v3_get_gic_config(void);
|
||||
extern u64 __vgic_v3_read_vmcr(void);
|
||||
extern void __vgic_v3_write_vmcr(u32 vmcr);
|
||||
extern void __vgic_v3_init_lrs(void);
|
||||
|
||||
@ -83,6 +83,11 @@ void sysreg_restore_guest_state_vhe(struct kvm_cpu_context *ctxt);
|
||||
void __debug_switch_to_guest(struct kvm_vcpu *vcpu);
|
||||
void __debug_switch_to_host(struct kvm_vcpu *vcpu);
|
||||
|
||||
#ifdef __KVM_NVHE_HYPERVISOR__
|
||||
void __debug_save_host_buffers_nvhe(struct kvm_vcpu *vcpu);
|
||||
void __debug_restore_host_buffers_nvhe(struct kvm_vcpu *vcpu);
|
||||
#endif
|
||||
|
||||
void __fpsimd_save_state(struct user_fpsimd_state *fp_regs);
|
||||
void __fpsimd_restore_state(struct user_fpsimd_state *fp_regs);
|
||||
|
||||
@ -97,7 +102,8 @@ bool kvm_host_psci_handler(struct kvm_cpu_context *host_ctxt);
|
||||
|
||||
void __noreturn hyp_panic(void);
|
||||
#ifdef __KVM_NVHE_HYPERVISOR__
|
||||
void __noreturn __hyp_do_panic(bool restore_host, u64 spsr, u64 elr, u64 par);
|
||||
void __noreturn __hyp_do_panic(struct kvm_cpu_context *host_ctxt, u64 spsr,
|
||||
u64 elr, u64 par);
|
||||
#endif
|
||||
|
||||
#endif /* __ARM64_KVM_HYP_H__ */
|
||||
|
||||
@ -328,6 +328,11 @@ static inline void *phys_to_virt(phys_addr_t x)
|
||||
#define ARCH_PFN_OFFSET ((unsigned long)PHYS_PFN_OFFSET)
|
||||
|
||||
#if !defined(CONFIG_SPARSEMEM_VMEMMAP) || defined(CONFIG_DEBUG_VIRTUAL)
|
||||
#define page_to_virt(x) ({ \
|
||||
__typeof__(x) __page = x; \
|
||||
void *__addr = __va(page_to_phys(__page)); \
|
||||
(void *)__tag_set((const void *)__addr, page_kasan_tag(__page));\
|
||||
})
|
||||
#define virt_to_page(x) pfn_to_page(virt_to_pfn(x))
|
||||
#else
|
||||
#define page_to_virt(x) ({ \
|
||||
|
||||
@ -63,23 +63,6 @@ static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm)
|
||||
extern u64 idmap_t0sz;
|
||||
extern u64 idmap_ptrs_per_pgd;
|
||||
|
||||
static inline bool __cpu_uses_extended_idmap(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_ARM64_VA_BITS_52))
|
||||
return false;
|
||||
|
||||
return unlikely(idmap_t0sz != TCR_T0SZ(VA_BITS));
|
||||
}
|
||||
|
||||
/*
|
||||
* True if the extended ID map requires an extra level of translation table
|
||||
* to be configured.
|
||||
*/
|
||||
static inline bool __cpu_uses_extended_idmap_level(void)
|
||||
{
|
||||
return ARM64_HW_PGTABLE_LEVELS(64 - idmap_t0sz) > CONFIG_PGTABLE_LEVELS;
|
||||
}
|
||||
|
||||
/*
|
||||
* Ensure TCR.T0SZ is set to the provided value.
|
||||
*/
|
||||
|
||||
@ -66,7 +66,6 @@ extern bool arm64_use_ng_mappings;
|
||||
#define _PAGE_DEFAULT (_PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
|
||||
|
||||
#define PAGE_KERNEL __pgprot(PROT_NORMAL)
|
||||
#define PAGE_KERNEL_TAGGED __pgprot(PROT_NORMAL_TAGGED)
|
||||
#define PAGE_KERNEL_RO __pgprot((PROT_NORMAL & ~PTE_WRITE) | PTE_RDONLY)
|
||||
#define PAGE_KERNEL_ROX __pgprot((PROT_NORMAL & ~(PTE_WRITE | PTE_PXN)) | PTE_RDONLY)
|
||||
#define PAGE_KERNEL_EXEC __pgprot(PROT_NORMAL & ~PTE_PXN)
|
||||
|
||||
@ -486,6 +486,9 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd)
|
||||
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
|
||||
#define pgprot_device(prot) \
|
||||
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
|
||||
#define pgprot_tagged(prot) \
|
||||
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED))
|
||||
#define pgprot_mhp pgprot_tagged
|
||||
/*
|
||||
* DMA allocations for non-coherent devices use what the Arm architecture calls
|
||||
* "Normal non-cacheable" memory, which permits speculation, unaligned accesses
|
||||
|
||||
@ -796,6 +796,11 @@
|
||||
#define ID_AA64MMFR0_PARANGE_48 0x5
|
||||
#define ID_AA64MMFR0_PARANGE_52 0x6
|
||||
|
||||
#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT 0x0
|
||||
#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE 0x1
|
||||
#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN 0x2
|
||||
#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX 0x7
|
||||
|
||||
#ifdef CONFIG_ARM64_PA_BITS_52
|
||||
#define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52
|
||||
#else
|
||||
@ -961,14 +966,17 @@
|
||||
#define ID_PFR1_PROGMOD_SHIFT 0
|
||||
|
||||
#if defined(CONFIG_ARM64_4K_PAGES)
|
||||
#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT
|
||||
#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED
|
||||
#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT
|
||||
#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN4_SUPPORTED
|
||||
#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 0x7
|
||||
#elif defined(CONFIG_ARM64_16K_PAGES)
|
||||
#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT
|
||||
#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED
|
||||
#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT
|
||||
#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN16_SUPPORTED
|
||||
#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 0xF
|
||||
#elif defined(CONFIG_ARM64_64K_PAGES)
|
||||
#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT
|
||||
#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED
|
||||
#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT
|
||||
#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN64_SUPPORTED
|
||||
#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 0x7
|
||||
#endif
|
||||
|
||||
#define MVFR2_FPMISC_SHIFT 4
|
||||
|
||||
@ -319,7 +319,7 @@ SYM_FUNC_START_LOCAL(__create_page_tables)
|
||||
*/
|
||||
adrp x5, __idmap_text_end
|
||||
clz x5, x5
|
||||
cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough?
|
||||
cmp x5, TCR_T0SZ(VA_BITS_MIN) // default T0SZ small enough?
|
||||
b.ge 1f // .. then skip VA range extension
|
||||
|
||||
adr_l x6, idmap_t0sz
|
||||
@ -655,8 +655,10 @@ SYM_FUNC_END(__secondary_too_slow)
|
||||
SYM_FUNC_START(__enable_mmu)
|
||||
mrs x2, ID_AA64MMFR0_EL1
|
||||
ubfx x2, x2, #ID_AA64MMFR0_TGRAN_SHIFT, 4
|
||||
cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED
|
||||
b.ne __no_granule_support
|
||||
cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED_MIN
|
||||
b.lt __no_granule_support
|
||||
cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED_MAX
|
||||
b.gt __no_granule_support
|
||||
update_early_cpu_boot_status 0, x2, x3
|
||||
adrp x2, idmap_pg_dir
|
||||
phys_to_ttbr x1, x1
|
||||
|
||||
@ -163,33 +163,36 @@ static __init void __parse_cmdline(const char *cmdline, bool parse_aliases)
|
||||
} while (1);
|
||||
}
|
||||
|
||||
static __init const u8 *get_bootargs_cmdline(void)
|
||||
{
|
||||
const u8 *prop;
|
||||
void *fdt;
|
||||
int node;
|
||||
|
||||
fdt = get_early_fdt_ptr();
|
||||
if (!fdt)
|
||||
return NULL;
|
||||
|
||||
node = fdt_path_offset(fdt, "/chosen");
|
||||
if (node < 0)
|
||||
return NULL;
|
||||
|
||||
prop = fdt_getprop(fdt, node, "bootargs", NULL);
|
||||
if (!prop)
|
||||
return NULL;
|
||||
|
||||
return strlen(prop) ? prop : NULL;
|
||||
}
|
||||
|
||||
static __init void parse_cmdline(void)
|
||||
{
|
||||
if (!IS_ENABLED(CONFIG_CMDLINE_FORCE)) {
|
||||
const u8 *prop;
|
||||
void *fdt;
|
||||
int node;
|
||||
const u8 *prop = get_bootargs_cmdline();
|
||||
|
||||
fdt = get_early_fdt_ptr();
|
||||
if (!fdt)
|
||||
goto out;
|
||||
|
||||
node = fdt_path_offset(fdt, "/chosen");
|
||||
if (node < 0)
|
||||
goto out;
|
||||
|
||||
prop = fdt_getprop(fdt, node, "bootargs", NULL);
|
||||
if (!prop)
|
||||
goto out;
|
||||
if (IS_ENABLED(CONFIG_CMDLINE_FORCE) || !prop)
|
||||
__parse_cmdline(CONFIG_CMDLINE, true);
|
||||
|
||||
if (!IS_ENABLED(CONFIG_CMDLINE_FORCE) && prop)
|
||||
__parse_cmdline(prop, true);
|
||||
|
||||
if (!IS_ENABLED(CONFIG_CMDLINE_EXTEND))
|
||||
return;
|
||||
}
|
||||
|
||||
out:
|
||||
__parse_cmdline(CONFIG_CMDLINE, true);
|
||||
}
|
||||
|
||||
/* Keep checkers quiet */
|
||||
|
||||
@ -101,6 +101,9 @@ KVM_NVHE_ALIAS(__stop___kvm_ex_table);
|
||||
/* Array containing bases of nVHE per-CPU memory regions. */
|
||||
KVM_NVHE_ALIAS(kvm_arm_hyp_percpu_base);
|
||||
|
||||
/* PMU available static key */
|
||||
KVM_NVHE_ALIAS(kvm_arm_pmu_available);
|
||||
|
||||
#endif /* CONFIG_KVM */
|
||||
|
||||
#endif /* __ARM64_KERNEL_IMAGE_VARS_H */
|
||||
|
||||
@ -460,7 +460,7 @@ static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
|
||||
return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
|
||||
}
|
||||
|
||||
static inline u32 armv8pmu_read_evcntr(int idx)
|
||||
static inline u64 armv8pmu_read_evcntr(int idx)
|
||||
{
|
||||
u32 counter = ARMV8_IDX_TO_COUNTER(idx);
|
||||
|
||||
|
||||
@ -385,11 +385,16 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
|
||||
last_ran = this_cpu_ptr(mmu->last_vcpu_ran);
|
||||
|
||||
/*
|
||||
* We guarantee that both TLBs and I-cache are private to each
|
||||
* vcpu. If detecting that a vcpu from the same VM has
|
||||
* previously run on the same physical CPU, call into the
|
||||
* hypervisor code to nuke the relevant contexts.
|
||||
*
|
||||
* We might get preempted before the vCPU actually runs, but
|
||||
* over-invalidation doesn't affect correctness.
|
||||
*/
|
||||
if (*last_ran != vcpu->vcpu_id) {
|
||||
kvm_call_hyp(__kvm_tlb_flush_local_vmid, mmu);
|
||||
kvm_call_hyp(__kvm_flush_cpu_context, mmu);
|
||||
*last_ran = vcpu->vcpu_id;
|
||||
}
|
||||
|
||||
|
||||
@ -85,8 +85,10 @@ SYM_INNER_LABEL(__guest_exit_panic, SYM_L_GLOBAL)
|
||||
|
||||
// If the hyp context is loaded, go straight to hyp_panic
|
||||
get_loaded_vcpu x0, x1
|
||||
cbz x0, hyp_panic
|
||||
cbnz x0, 1f
|
||||
b hyp_panic
|
||||
|
||||
1:
|
||||
// The hyp context is saved so make sure it is restored to allow
|
||||
// hyp_panic to run at hyp and, subsequently, panic to run in the host.
|
||||
// This makes use of __guest_exit to avoid duplication but sets the
|
||||
@ -94,7 +96,7 @@ SYM_INNER_LABEL(__guest_exit_panic, SYM_L_GLOBAL)
|
||||
// current state is saved to the guest context but it will only be
|
||||
// accurate if the guest had been completely restored.
|
||||
adr_this_cpu x0, kvm_hyp_ctxt, x1
|
||||
adr x1, hyp_panic
|
||||
adr_l x1, hyp_panic
|
||||
str x1, [x0, #CPU_XREG_OFFSET(30)]
|
||||
|
||||
get_vcpu_ptr x1, x0
|
||||
@ -146,7 +148,7 @@ SYM_INNER_LABEL(__guest_exit, SYM_L_GLOBAL)
|
||||
// Now restore the hyp regs
|
||||
restore_callee_saved_regs x2
|
||||
|
||||
set_loaded_vcpu xzr, x1, x2
|
||||
set_loaded_vcpu xzr, x2, x3
|
||||
|
||||
alternative_if ARM64_HAS_RAS_EXTN
|
||||
// If we have the RAS extensions we can consume a pending error
|
||||
|
||||
@ -90,15 +90,18 @@ static inline void __activate_traps_common(struct kvm_vcpu *vcpu)
|
||||
* counter, which could make a PMXEVCNTR_EL0 access UNDEF at
|
||||
* EL1 instead of being trapped to EL2.
|
||||
*/
|
||||
write_sysreg(0, pmselr_el0);
|
||||
write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
|
||||
if (kvm_arm_support_pmu_v3()) {
|
||||
write_sysreg(0, pmselr_el0);
|
||||
write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
|
||||
}
|
||||
write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
|
||||
}
|
||||
|
||||
static inline void __deactivate_traps_common(void)
|
||||
{
|
||||
write_sysreg(0, hstr_el2);
|
||||
write_sysreg(0, pmuserenr_el0);
|
||||
if (kvm_arm_support_pmu_v3())
|
||||
write_sysreg(0, pmuserenr_el0);
|
||||
}
|
||||
|
||||
static inline void ___activate_traps(struct kvm_vcpu *vcpu)
|
||||
|
||||
@ -58,16 +58,24 @@ static void __debug_restore_spe(u64 pmscr_el1)
|
||||
write_sysreg_s(pmscr_el1, SYS_PMSCR_EL1);
|
||||
}
|
||||
|
||||
void __debug_switch_to_guest(struct kvm_vcpu *vcpu)
|
||||
void __debug_save_host_buffers_nvhe(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
/* Disable and flush SPE data generation */
|
||||
__debug_save_spe(&vcpu->arch.host_debug_state.pmscr_el1);
|
||||
}
|
||||
|
||||
void __debug_switch_to_guest(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
__debug_switch_to_guest_common(vcpu);
|
||||
}
|
||||
|
||||
void __debug_restore_host_buffers_nvhe(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
__debug_restore_spe(vcpu->arch.host_debug_state.pmscr_el1);
|
||||
}
|
||||
|
||||
void __debug_switch_to_host(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
__debug_restore_spe(vcpu->arch.host_debug_state.pmscr_el1);
|
||||
__debug_switch_to_host_common(vcpu);
|
||||
}
|
||||
|
||||
|
||||
@ -71,7 +71,8 @@ SYM_FUNC_START(__host_enter)
|
||||
SYM_FUNC_END(__host_enter)
|
||||
|
||||
/*
|
||||
* void __noreturn __hyp_do_panic(bool restore_host, u64 spsr, u64 elr, u64 par);
|
||||
* void __noreturn __hyp_do_panic(struct kvm_cpu_context *host_ctxt, u64 spsr,
|
||||
* u64 elr, u64 par);
|
||||
*/
|
||||
SYM_FUNC_START(__hyp_do_panic)
|
||||
/* Prepare and exit to the host's panic funciton. */
|
||||
@ -82,9 +83,11 @@ SYM_FUNC_START(__hyp_do_panic)
|
||||
hyp_kimg_va lr, x6
|
||||
msr elr_el2, lr
|
||||
|
||||
/* Set the panic format string. Use the, now free, LR as scratch. */
|
||||
ldr lr, =__hyp_panic_string
|
||||
hyp_kimg_va lr, x6
|
||||
mov x29, x0
|
||||
|
||||
/* Load the format string into x0 and arguments into x1-7 */
|
||||
ldr x0, =__hyp_panic_string
|
||||
hyp_kimg_va x0, x6
|
||||
|
||||
/* Load the format arguments into x1-7. */
|
||||
mov x6, x3
|
||||
@ -94,9 +97,7 @@ SYM_FUNC_START(__hyp_do_panic)
|
||||
mrs x5, hpfar_el2
|
||||
|
||||
/* Enter the host, conditionally restoring the host context. */
|
||||
cmp x0, xzr
|
||||
mov x0, lr
|
||||
b.eq __host_enter_without_restoring
|
||||
cbz x29, __host_enter_without_restoring
|
||||
b __host_enter_for_panic
|
||||
SYM_FUNC_END(__hyp_do_panic)
|
||||
|
||||
|
||||
@ -46,11 +46,11 @@ static void handle___kvm_tlb_flush_vmid(struct kvm_cpu_context *host_ctxt)
|
||||
__kvm_tlb_flush_vmid(kern_hyp_va(mmu));
|
||||
}
|
||||
|
||||
static void handle___kvm_tlb_flush_local_vmid(struct kvm_cpu_context *host_ctxt)
|
||||
static void handle___kvm_flush_cpu_context(struct kvm_cpu_context *host_ctxt)
|
||||
{
|
||||
DECLARE_REG(struct kvm_s2_mmu *, mmu, host_ctxt, 1);
|
||||
|
||||
__kvm_tlb_flush_local_vmid(kern_hyp_va(mmu));
|
||||
__kvm_flush_cpu_context(kern_hyp_va(mmu));
|
||||
}
|
||||
|
||||
static void handle___kvm_timer_set_cntvoff(struct kvm_cpu_context *host_ctxt)
|
||||
@ -67,9 +67,9 @@ static void handle___kvm_enable_ssbs(struct kvm_cpu_context *host_ctxt)
|
||||
write_sysreg_el2(tmp, SYS_SCTLR);
|
||||
}
|
||||
|
||||
static void handle___vgic_v3_get_ich_vtr_el2(struct kvm_cpu_context *host_ctxt)
|
||||
static void handle___vgic_v3_get_gic_config(struct kvm_cpu_context *host_ctxt)
|
||||
{
|
||||
cpu_reg(host_ctxt, 1) = __vgic_v3_get_ich_vtr_el2();
|
||||
cpu_reg(host_ctxt, 1) = __vgic_v3_get_gic_config();
|
||||
}
|
||||
|
||||
static void handle___vgic_v3_read_vmcr(struct kvm_cpu_context *host_ctxt)
|
||||
@ -115,10 +115,10 @@ static const hcall_t host_hcall[] = {
|
||||
HANDLE_FUNC(__kvm_flush_vm_context),
|
||||
HANDLE_FUNC(__kvm_tlb_flush_vmid_ipa),
|
||||
HANDLE_FUNC(__kvm_tlb_flush_vmid),
|
||||
HANDLE_FUNC(__kvm_tlb_flush_local_vmid),
|
||||
HANDLE_FUNC(__kvm_flush_cpu_context),
|
||||
HANDLE_FUNC(__kvm_timer_set_cntvoff),
|
||||
HANDLE_FUNC(__kvm_enable_ssbs),
|
||||
HANDLE_FUNC(__vgic_v3_get_ich_vtr_el2),
|
||||
HANDLE_FUNC(__vgic_v3_get_gic_config),
|
||||
HANDLE_FUNC(__vgic_v3_read_vmcr),
|
||||
HANDLE_FUNC(__vgic_v3_write_vmcr),
|
||||
HANDLE_FUNC(__vgic_v3_init_lrs),
|
||||
|
||||
@ -192,6 +192,14 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
|
||||
pmu_switch_needed = __pmu_switch_to_guest(host_ctxt);
|
||||
|
||||
__sysreg_save_state_nvhe(host_ctxt);
|
||||
/*
|
||||
* We must flush and disable the SPE buffer for nVHE, as
|
||||
* the translation regime(EL1&0) is going to be loaded with
|
||||
* that of the guest. And we must do this before we change the
|
||||
* translation regime to EL2 (via MDCR_EL2_E2PB == 0) and
|
||||
* before we load guest Stage1.
|
||||
*/
|
||||
__debug_save_host_buffers_nvhe(vcpu);
|
||||
|
||||
__adjust_pc(vcpu);
|
||||
|
||||
@ -234,11 +242,12 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
|
||||
if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)
|
||||
__fpsimd_save_fpexc32(vcpu);
|
||||
|
||||
__debug_switch_to_host(vcpu);
|
||||
/*
|
||||
* This must come after restoring the host sysregs, since a non-VHE
|
||||
* system may enable SPE here and make use of the TTBRs.
|
||||
*/
|
||||
__debug_switch_to_host(vcpu);
|
||||
__debug_restore_host_buffers_nvhe(vcpu);
|
||||
|
||||
if (pmu_switch_needed)
|
||||
__pmu_switch_to_host(host_ctxt);
|
||||
@ -257,7 +266,6 @@ void __noreturn hyp_panic(void)
|
||||
u64 spsr = read_sysreg_el2(SYS_SPSR);
|
||||
u64 elr = read_sysreg_el2(SYS_ELR);
|
||||
u64 par = read_sysreg_par();
|
||||
bool restore_host = true;
|
||||
struct kvm_cpu_context *host_ctxt;
|
||||
struct kvm_vcpu *vcpu;
|
||||
|
||||
@ -271,7 +279,7 @@ void __noreturn hyp_panic(void)
|
||||
__sysreg_restore_state_nvhe(host_ctxt);
|
||||
}
|
||||
|
||||
__hyp_do_panic(restore_host, spsr, elr, par);
|
||||
__hyp_do_panic(host_ctxt, spsr, elr, par);
|
||||
unreachable();
|
||||
}
|
||||
|
||||
|
||||
@ -123,7 +123,7 @@ void __kvm_tlb_flush_vmid(struct kvm_s2_mmu *mmu)
|
||||
__tlb_switch_to_host(&cxt);
|
||||
}
|
||||
|
||||
void __kvm_tlb_flush_local_vmid(struct kvm_s2_mmu *mmu)
|
||||
void __kvm_flush_cpu_context(struct kvm_s2_mmu *mmu)
|
||||
{
|
||||
struct tlb_inv_context cxt;
|
||||
|
||||
@ -131,6 +131,7 @@ void __kvm_tlb_flush_local_vmid(struct kvm_s2_mmu *mmu)
|
||||
__tlb_switch_to_guest(mmu, &cxt);
|
||||
|
||||
__tlbi(vmalle1);
|
||||
asm volatile("ic iallu");
|
||||
dsb(nsh);
|
||||
isb();
|
||||
|
||||
|
||||
@ -223,6 +223,7 @@ static inline int __kvm_pgtable_visit(struct kvm_pgtable_walk_data *data,
|
||||
goto out;
|
||||
|
||||
if (!table) {
|
||||
data->addr = ALIGN_DOWN(data->addr, kvm_granule_size(level));
|
||||
data->addr += kvm_granule_size(level);
|
||||
goto out;
|
||||
}
|
||||
|
||||
@ -405,9 +405,45 @@ void __vgic_v3_init_lrs(void)
|
||||
__gic_v3_set_lr(0, i);
|
||||
}
|
||||
|
||||
u64 __vgic_v3_get_ich_vtr_el2(void)
|
||||
/*
|
||||
* Return the GIC CPU configuration:
|
||||
* - [31:0] ICH_VTR_EL2
|
||||
* - [62:32] RES0
|
||||
* - [63] MMIO (GICv2) capable
|
||||
*/
|
||||
u64 __vgic_v3_get_gic_config(void)
|
||||
{
|
||||
return read_gicreg(ICH_VTR_EL2);
|
||||
u64 val, sre = read_gicreg(ICC_SRE_EL1);
|
||||
unsigned long flags = 0;
|
||||
|
||||
/*
|
||||
* To check whether we have a MMIO-based (GICv2 compatible)
|
||||
* CPU interface, we need to disable the system register
|
||||
* view. To do that safely, we have to prevent any interrupt
|
||||
* from firing (which would be deadly).
|
||||
*
|
||||
* Note that this only makes sense on VHE, as interrupts are
|
||||
* already masked for nVHE as part of the exception entry to
|
||||
* EL2.
|
||||
*/
|
||||
if (has_vhe())
|
||||
flags = local_daif_save();
|
||||
|
||||
write_gicreg(0, ICC_SRE_EL1);
|
||||
isb();
|
||||
|
||||
val = read_gicreg(ICC_SRE_EL1);
|
||||
|
||||
write_gicreg(sre, ICC_SRE_EL1);
|
||||
isb();
|
||||
|
||||
if (has_vhe())
|
||||
local_daif_restore(flags);
|
||||
|
||||
val = (val & ICC_SRE_EL1_SRE) ? 0 : (1ULL << 63);
|
||||
val |= read_gicreg(ICH_VTR_EL2);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
u64 __vgic_v3_read_vmcr(void)
|
||||
|
||||
@ -127,7 +127,7 @@ void __kvm_tlb_flush_vmid(struct kvm_s2_mmu *mmu)
|
||||
__tlb_switch_to_host(&cxt);
|
||||
}
|
||||
|
||||
void __kvm_tlb_flush_local_vmid(struct kvm_s2_mmu *mmu)
|
||||
void __kvm_flush_cpu_context(struct kvm_s2_mmu *mmu)
|
||||
{
|
||||
struct tlb_inv_context cxt;
|
||||
|
||||
@ -135,6 +135,7 @@ void __kvm_tlb_flush_local_vmid(struct kvm_s2_mmu *mmu)
|
||||
__tlb_switch_to_guest(mmu, &cxt);
|
||||
|
||||
__tlbi(vmalle1);
|
||||
asm volatile("ic iallu");
|
||||
dsb(nsh);
|
||||
isb();
|
||||
|
||||
|
||||
@ -1312,8 +1312,7 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm,
|
||||
* Prevent userspace from creating a memory region outside of the IPA
|
||||
* space addressable by the KVM guest IPA space.
|
||||
*/
|
||||
if (memslot->base_gfn + memslot->npages >=
|
||||
(kvm_phys_size(kvm) >> PAGE_SHIFT))
|
||||
if ((memslot->base_gfn + memslot->npages) > (kvm_phys_size(kvm) >> PAGE_SHIFT))
|
||||
return -EFAULT;
|
||||
|
||||
mmap_read_lock(current->mm);
|
||||
|
||||
@ -11,6 +11,8 @@
|
||||
|
||||
#include <asm/kvm_emulate.h>
|
||||
|
||||
DEFINE_STATIC_KEY_FALSE(kvm_arm_pmu_available);
|
||||
|
||||
static int kvm_is_in_guest(void)
|
||||
{
|
||||
return kvm_get_running_vcpu() != NULL;
|
||||
@ -48,6 +50,14 @@ static struct perf_guest_info_callbacks kvm_guest_cbs = {
|
||||
|
||||
int kvm_perf_init(void)
|
||||
{
|
||||
/*
|
||||
* Check if HW_PERF_EVENTS are supported by checking the number of
|
||||
* hardware performance counters. This could ensure the presence of
|
||||
* a physical PMU and CONFIG_PERF_EVENT is selected.
|
||||
*/
|
||||
if (IS_ENABLED(CONFIG_ARM_PMU) && perf_num_counters() > 0)
|
||||
static_branch_enable(&kvm_arm_pmu_available);
|
||||
|
||||
return perf_register_guest_info_callbacks(&kvm_guest_cbs);
|
||||
}
|
||||
|
||||
|
||||
@ -823,16 +823,6 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1)
|
||||
return val & mask;
|
||||
}
|
||||
|
||||
bool kvm_arm_support_pmu_v3(void)
|
||||
{
|
||||
/*
|
||||
* Check if HW_PERF_EVENTS are supported by checking the number of
|
||||
* hardware performance counters. This could ensure the presence of
|
||||
* a physical PMU and CONFIG_PERF_EVENT is selected.
|
||||
*/
|
||||
return (perf_num_counters() > 0);
|
||||
}
|
||||
|
||||
int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
if (!kvm_vcpu_has_pmu(vcpu))
|
||||
|
||||
@ -311,23 +311,24 @@ int kvm_set_ipa_limit(void)
|
||||
}
|
||||
|
||||
switch (cpuid_feature_extract_unsigned_field(mmfr0, tgran_2)) {
|
||||
default:
|
||||
case 1:
|
||||
case ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE:
|
||||
kvm_err("PAGE_SIZE not supported at Stage-2, giving up\n");
|
||||
return -EINVAL;
|
||||
case 0:
|
||||
case ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT:
|
||||
kvm_debug("PAGE_SIZE supported at Stage-2 (default)\n");
|
||||
break;
|
||||
case 2:
|
||||
case ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN ... ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX:
|
||||
kvm_debug("PAGE_SIZE supported at Stage-2 (advertised)\n");
|
||||
break;
|
||||
default:
|
||||
kvm_err("Unsupported value for TGRAN_2, giving up\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
kvm_ipa_limit = id_aa64mmfr0_parange_to_phys_shift(parange);
|
||||
WARN(kvm_ipa_limit < KVM_PHYS_SHIFT,
|
||||
"KVM IPA Size Limit (%d bits) is smaller than default size\n",
|
||||
kvm_ipa_limit);
|
||||
kvm_info("IPA Size Limit: %d bits\n", kvm_ipa_limit);
|
||||
kvm_info("IPA Size Limit: %d bits%s\n", kvm_ipa_limit,
|
||||
((kvm_ipa_limit < KVM_PHYS_SHIFT) ?
|
||||
" (Reduced IPA size, limited VM/VMM compatibility)" : ""));
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -356,6 +357,11 @@ int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type)
|
||||
return -EINVAL;
|
||||
} else {
|
||||
phys_shift = KVM_PHYS_SHIFT;
|
||||
if (phys_shift > kvm_ipa_limit) {
|
||||
pr_warn_once("%s using unsupported default IPA limit, upgrade your VMM\n",
|
||||
current->comm);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
|
||||
|
||||
@ -574,9 +574,13 @@ early_param("kvm-arm.vgic_v4_enable", early_gicv4_enable);
|
||||
*/
|
||||
int vgic_v3_probe(const struct gic_kvm_info *info)
|
||||
{
|
||||
u32 ich_vtr_el2 = kvm_call_hyp_ret(__vgic_v3_get_ich_vtr_el2);
|
||||
u64 ich_vtr_el2 = kvm_call_hyp_ret(__vgic_v3_get_gic_config);
|
||||
bool has_v2;
|
||||
int ret;
|
||||
|
||||
has_v2 = ich_vtr_el2 >> 63;
|
||||
ich_vtr_el2 = (u32)ich_vtr_el2;
|
||||
|
||||
/*
|
||||
* The ListRegs field is 5 bits, but there is an architectural
|
||||
* maximum of 16 list registers. Just ignore bit 4...
|
||||
@ -594,13 +598,15 @@ int vgic_v3_probe(const struct gic_kvm_info *info)
|
||||
gicv4_enable ? "en" : "dis");
|
||||
}
|
||||
|
||||
kvm_vgic_global_state.vcpu_base = 0;
|
||||
|
||||
if (!info->vcpu.start) {
|
||||
kvm_info("GICv3: no GICV resource entry\n");
|
||||
kvm_vgic_global_state.vcpu_base = 0;
|
||||
} else if (!has_v2) {
|
||||
pr_warn(FW_BUG "CPU interface incapable of MMIO access\n");
|
||||
} else if (!PAGE_ALIGNED(info->vcpu.start)) {
|
||||
pr_warn("GICV physical address 0x%llx not page aligned\n",
|
||||
(unsigned long long)info->vcpu.start);
|
||||
kvm_vgic_global_state.vcpu_base = 0;
|
||||
} else {
|
||||
kvm_vgic_global_state.vcpu_base = info->vcpu.start;
|
||||
kvm_vgic_global_state.can_emulate_gicv2 = true;
|
||||
|
||||
@ -219,17 +219,40 @@ static void __init zone_sizes_init(unsigned long min, unsigned long max)
|
||||
|
||||
int pfn_valid(unsigned long pfn)
|
||||
{
|
||||
phys_addr_t addr = pfn << PAGE_SHIFT;
|
||||
phys_addr_t addr = PFN_PHYS(pfn);
|
||||
|
||||
if ((addr >> PAGE_SHIFT) != pfn)
|
||||
/*
|
||||
* Ensure the upper PAGE_SHIFT bits are clear in the
|
||||
* pfn. Else it might lead to false positives when
|
||||
* some of the upper bits are set, but the lower bits
|
||||
* match a valid pfn.
|
||||
*/
|
||||
if (PHYS_PFN(addr) != pfn)
|
||||
return 0;
|
||||
|
||||
#ifdef CONFIG_SPARSEMEM
|
||||
{
|
||||
struct mem_section *ms;
|
||||
|
||||
if (pfn_to_section_nr(pfn) >= NR_MEM_SECTIONS)
|
||||
return 0;
|
||||
|
||||
if (!valid_section(__pfn_to_section(pfn)))
|
||||
ms = __pfn_to_section(pfn);
|
||||
if (!valid_section(ms))
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* ZONE_DEVICE memory does not have the memblock entries.
|
||||
* memblock_is_map_memory() check for ZONE_DEVICE based
|
||||
* addresses will always fail. Even the normal hotplugged
|
||||
* memory will never have MEMBLOCK_NOMAP flag set in their
|
||||
* memblock entries. Skip memblock search for all non early
|
||||
* memory sections covering all of hotplug memory including
|
||||
* both normal and ZONE_DEVICE based.
|
||||
*/
|
||||
if (!early_section(ms))
|
||||
return pfn_section_valid(ms, pfn);
|
||||
}
|
||||
#endif
|
||||
return memblock_is_map_memory(addr);
|
||||
}
|
||||
|
||||
@ -40,7 +40,7 @@
|
||||
#define NO_BLOCK_MAPPINGS BIT(0)
|
||||
#define NO_CONT_MAPPINGS BIT(1)
|
||||
|
||||
u64 idmap_t0sz = TCR_T0SZ(VA_BITS);
|
||||
u64 idmap_t0sz = TCR_T0SZ(VA_BITS_MIN);
|
||||
u64 idmap_ptrs_per_pgd = PTRS_PER_PGD;
|
||||
|
||||
u64 __section(".mmuoff.data.write") vabits_actual;
|
||||
@ -512,7 +512,8 @@ static void __init map_mem(pgd_t *pgdp)
|
||||
* if MTE is present. Otherwise, it has the same attributes as
|
||||
* PAGE_KERNEL.
|
||||
*/
|
||||
__map_memblock(pgdp, start, end, PAGE_KERNEL_TAGGED, flags);
|
||||
__map_memblock(pgdp, start, end, pgprot_tagged(PAGE_KERNEL),
|
||||
flags);
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@ -32,7 +32,7 @@ static inline void syscall_rollback(struct task_struct *task,
|
||||
static inline long syscall_get_error(struct task_struct *task,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
return regs->r10 == -1 ? regs->r8:0;
|
||||
return regs->r10 == -1 ? -regs->r8:0;
|
||||
}
|
||||
|
||||
static inline long syscall_get_return_value(struct task_struct *task,
|
||||
|
||||
@ -2013,27 +2013,39 @@ static void syscall_get_set_args_cb(struct unw_frame_info *info, void *data)
|
||||
{
|
||||
struct syscall_get_set_args *args = data;
|
||||
struct pt_regs *pt = args->regs;
|
||||
unsigned long *krbs, cfm, ndirty;
|
||||
unsigned long *krbs, cfm, ndirty, nlocals, nouts;
|
||||
int i, count;
|
||||
|
||||
if (unw_unwind_to_user(info) < 0)
|
||||
return;
|
||||
|
||||
/*
|
||||
* We get here via a few paths:
|
||||
* - break instruction: cfm is shared with caller.
|
||||
* syscall args are in out= regs, locals are non-empty.
|
||||
* - epsinstruction: cfm is set by br.call
|
||||
* locals don't exist.
|
||||
*
|
||||
* For both cases argguments are reachable in cfm.sof - cfm.sol.
|
||||
* CFM: [ ... | sor: 17..14 | sol : 13..7 | sof : 6..0 ]
|
||||
*/
|
||||
cfm = pt->cr_ifs;
|
||||
nlocals = (cfm >> 7) & 0x7f; /* aka sol */
|
||||
nouts = (cfm & 0x7f) - nlocals; /* aka sof - sol */
|
||||
krbs = (unsigned long *)info->task + IA64_RBS_OFFSET/8;
|
||||
ndirty = ia64_rse_num_regs(krbs, krbs + (pt->loadrs >> 19));
|
||||
|
||||
count = 0;
|
||||
if (in_syscall(pt))
|
||||
count = min_t(int, args->n, cfm & 0x7f);
|
||||
count = min_t(int, args->n, nouts);
|
||||
|
||||
/* Iterate over outs. */
|
||||
for (i = 0; i < count; i++) {
|
||||
int j = ndirty + nlocals + i + args->i;
|
||||
if (args->rw)
|
||||
*ia64_rse_skip_regs(krbs, ndirty + i + args->i) =
|
||||
args->args[i];
|
||||
*ia64_rse_skip_regs(krbs, j) = args->args[i];
|
||||
else
|
||||
args->args[i] = *ia64_rse_skip_regs(krbs,
|
||||
ndirty + i + args->i);
|
||||
args->args[i] = *ia64_rse_skip_regs(krbs, j);
|
||||
}
|
||||
|
||||
if (!args->rw) {
|
||||
|
||||
@ -171,7 +171,7 @@ static inline __attribute_const__ int __virt_to_node_shift(void)
|
||||
#include <asm-generic/memory_model.h>
|
||||
#endif
|
||||
|
||||
#define virt_addr_valid(kaddr) ((void *)(kaddr) >= (void *)PAGE_OFFSET && (void *)(kaddr) < high_memory)
|
||||
#define virt_addr_valid(kaddr) ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory)
|
||||
#define pfn_valid(pfn) virt_addr_valid(pfn_to_virt(pfn))
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
@ -30,8 +30,8 @@ extern unsigned long memory_end;
|
||||
#define page_to_pfn(page) virt_to_pfn(page_to_virt(page))
|
||||
#define pfn_valid(pfn) ((pfn) < max_mapnr)
|
||||
|
||||
#define virt_addr_valid(kaddr) (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \
|
||||
((void *)(kaddr) < (void *)memory_end))
|
||||
#define virt_addr_valid(kaddr) (((unsigned long)(kaddr) >= PAGE_OFFSET) && \
|
||||
((unsigned long)(kaddr) < memory_end))
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
|
||||
@ -14,6 +14,7 @@
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/unaligned.h>
|
||||
#include <asm-generic/vmlinux.lds.h>
|
||||
|
||||
/*
|
||||
* These two variables specify the free mem region
|
||||
@ -120,6 +121,13 @@ void decompress_kernel(unsigned long boot_heap_start)
|
||||
/* last four bytes is always image size in little endian */
|
||||
image_size = get_unaligned_le32((void *)&__image_end - 4);
|
||||
|
||||
/* The device tree's address must be properly aligned */
|
||||
image_size = ALIGN(image_size, STRUCT_ALIGNMENT);
|
||||
|
||||
puts("Copy device tree to address ");
|
||||
puthex(VMLINUX_LOAD_ADDRESS_ULL + image_size);
|
||||
puts("\n");
|
||||
|
||||
/* copy dtb to where the booted kernel will expect it */
|
||||
memcpy((void *)VMLINUX_LOAD_ADDRESS_ULL + image_size,
|
||||
__appended_dtb, dtb_size);
|
||||
|
||||
@ -12,8 +12,8 @@ AFLAGS_chacha-core.o += -O2 # needed to fill branch delay slots
|
||||
obj-$(CONFIG_CRYPTO_POLY1305_MIPS) += poly1305-mips.o
|
||||
poly1305-mips-y := poly1305-core.o poly1305-glue.o
|
||||
|
||||
perlasm-flavour-$(CONFIG_CPU_MIPS32) := o32
|
||||
perlasm-flavour-$(CONFIG_CPU_MIPS64) := 64
|
||||
perlasm-flavour-$(CONFIG_32BIT) := o32
|
||||
perlasm-flavour-$(CONFIG_64BIT) := 64
|
||||
|
||||
quiet_cmd_perlasm = PERLASM $@
|
||||
cmd_perlasm = $(PERL) $(<) $(perlasm-flavour-y) $(@)
|
||||
|
||||
@ -24,8 +24,11 @@ extern void (*board_ebase_setup)(void);
|
||||
extern void (*board_cache_error_setup)(void);
|
||||
|
||||
extern int register_nmi_notifier(struct notifier_block *nb);
|
||||
extern void reserve_exception_space(phys_addr_t addr, unsigned long size);
|
||||
extern char except_vec_nmi[];
|
||||
|
||||
#define VECTORSPACING 0x100 /* for EI/VI mode */
|
||||
|
||||
#define nmi_notifier(fn, pri) \
|
||||
({ \
|
||||
static struct notifier_block fn##_nb = { \
|
||||
|
||||
@ -26,6 +26,7 @@
|
||||
#include <asm/elf.h>
|
||||
#include <asm/pgtable-bits.h>
|
||||
#include <asm/spram.h>
|
||||
#include <asm/traps.h>
|
||||
#include <linux/uaccess.h>
|
||||
|
||||
#include "fpu-probe.h"
|
||||
@ -1628,6 +1629,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
|
||||
c->cputype = CPU_BMIPS3300;
|
||||
__cpu_name[cpu] = "Broadcom BMIPS3300";
|
||||
set_elf_platform(cpu, "bmips3300");
|
||||
reserve_exception_space(0x400, VECTORSPACING * 64);
|
||||
break;
|
||||
case PRID_IMP_BMIPS43XX: {
|
||||
int rev = c->processor_id & PRID_REV_MASK;
|
||||
@ -1638,6 +1640,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
|
||||
__cpu_name[cpu] = "Broadcom BMIPS4380";
|
||||
set_elf_platform(cpu, "bmips4380");
|
||||
c->options |= MIPS_CPU_RIXI;
|
||||
reserve_exception_space(0x400, VECTORSPACING * 64);
|
||||
} else {
|
||||
c->cputype = CPU_BMIPS4350;
|
||||
__cpu_name[cpu] = "Broadcom BMIPS4350";
|
||||
@ -1654,6 +1657,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
|
||||
__cpu_name[cpu] = "Broadcom BMIPS5000";
|
||||
set_elf_platform(cpu, "bmips5000");
|
||||
c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
|
||||
reserve_exception_space(0x1000, VECTORSPACING * 64);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -2133,6 +2137,8 @@ void cpu_probe(void)
|
||||
if (cpu == 0)
|
||||
__ua_limit = ~((1ull << cpu_vmbits) - 1);
|
||||
#endif
|
||||
|
||||
reserve_exception_space(0, 0x1000);
|
||||
}
|
||||
|
||||
void cpu_report(void)
|
||||
|
||||
@ -21,6 +21,7 @@
|
||||
#include <asm/fpu.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/elf.h>
|
||||
#include <asm/traps.h>
|
||||
|
||||
#include "fpu-probe.h"
|
||||
|
||||
@ -158,6 +159,8 @@ void cpu_probe(void)
|
||||
cpu_set_fpu_opts(c);
|
||||
else
|
||||
cpu_set_nofpu_opts(c);
|
||||
|
||||
reserve_exception_space(0, 0x400);
|
||||
}
|
||||
|
||||
void cpu_report(void)
|
||||
|
||||
@ -2009,13 +2009,16 @@ void __noreturn nmi_exception_handler(struct pt_regs *regs)
|
||||
nmi_exit();
|
||||
}
|
||||
|
||||
#define VECTORSPACING 0x100 /* for EI/VI mode */
|
||||
|
||||
unsigned long ebase;
|
||||
EXPORT_SYMBOL_GPL(ebase);
|
||||
unsigned long exception_handlers[32];
|
||||
unsigned long vi_handlers[64];
|
||||
|
||||
void reserve_exception_space(phys_addr_t addr, unsigned long size)
|
||||
{
|
||||
memblock_reserve(addr, size);
|
||||
}
|
||||
|
||||
void __init *set_except_vector(int n, void *addr)
|
||||
{
|
||||
unsigned long handler = (unsigned long) addr;
|
||||
@ -2367,10 +2370,7 @@ void __init trap_init(void)
|
||||
|
||||
if (!cpu_has_mips_r2_r6) {
|
||||
ebase = CAC_BASE;
|
||||
ebase_pa = virt_to_phys((void *)ebase);
|
||||
vec_size = 0x400;
|
||||
|
||||
memblock_reserve(ebase_pa, vec_size);
|
||||
} else {
|
||||
if (cpu_has_veic || cpu_has_vint)
|
||||
vec_size = 0x200 + VECTORSPACING*64;
|
||||
|
||||
@ -145,6 +145,7 @@ SECTIONS
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MIPS_ELF_APPENDED_DTB
|
||||
STRUCT_ALIGN();
|
||||
.appended_dtb : AT(ADDR(.appended_dtb) - LOAD_OFFSET) {
|
||||
*(.appended_dtb)
|
||||
KEEP(*(.appended_dtb))
|
||||
@ -172,6 +173,11 @@ SECTIONS
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MIPS_RAW_APPENDED_DTB
|
||||
.fill : {
|
||||
FILL(0);
|
||||
BYTE(0);
|
||||
. = ALIGN(8);
|
||||
}
|
||||
__appended_dtb = .;
|
||||
/* leave space for appended DTB */
|
||||
. += 0x100000;
|
||||
|
||||
@ -203,9 +203,12 @@ config PREFETCH
|
||||
def_bool y
|
||||
depends on PA8X00 || PA7200
|
||||
|
||||
config PARISC_HUGE_KERNEL
|
||||
def_bool y if !MODULES || UBSAN || FTRACE || COMPILE_TEST
|
||||
|
||||
config MLONGCALLS
|
||||
def_bool y if !MODULES || UBSAN || FTRACE
|
||||
bool "Enable the -mlong-calls compiler option for big kernels" if MODULES && !UBSAN && !FTRACE
|
||||
def_bool y if PARISC_HUGE_KERNEL
|
||||
bool "Enable the -mlong-calls compiler option for big kernels" if !PARISC_HUGE_KERNEL
|
||||
depends on PA8X00
|
||||
help
|
||||
If you configure the kernel to include many drivers built-in instead
|
||||
|
||||
@ -567,8 +567,6 @@ static const struct user_regset_view user_parisc_native_view = {
|
||||
};
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
#include <linux/compat.h>
|
||||
|
||||
static int gpr32_get(struct task_struct *target,
|
||||
const struct user_regset *regset,
|
||||
struct membuf to)
|
||||
|
||||
@ -73,9 +73,10 @@ void __patch_exception(int exc, unsigned long addr);
|
||||
#endif
|
||||
|
||||
#define OP_RT_RA_MASK 0xffff0000UL
|
||||
#define LIS_R2 0x3c020000UL
|
||||
#define ADDIS_R2_R12 0x3c4c0000UL
|
||||
#define ADDI_R2_R2 0x38420000UL
|
||||
#define LIS_R2 (PPC_INST_ADDIS | __PPC_RT(R2))
|
||||
#define ADDIS_R2_R12 (PPC_INST_ADDIS | __PPC_RT(R2) | __PPC_RA(R12))
|
||||
#define ADDI_R2_R2 (PPC_INST_ADDI | __PPC_RT(R2) | __PPC_RA(R2))
|
||||
|
||||
|
||||
static inline unsigned long ppc_function_entry(void *func)
|
||||
{
|
||||
|
||||
@ -53,8 +53,8 @@ static inline void mtdcrx(unsigned int reg, unsigned int val)
|
||||
#define mfdcr(rn) \
|
||||
({unsigned int rval; \
|
||||
if (__builtin_constant_p(rn) && rn < 1024) \
|
||||
asm volatile("mfdcr %0," __stringify(rn) \
|
||||
: "=r" (rval)); \
|
||||
asm volatile("mfdcr %0, %1" : "=r" (rval) \
|
||||
: "n" (rn)); \
|
||||
else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR))) \
|
||||
rval = mfdcrx(rn); \
|
||||
else \
|
||||
@ -64,8 +64,8 @@ static inline void mtdcrx(unsigned int reg, unsigned int val)
|
||||
#define mtdcr(rn, v) \
|
||||
do { \
|
||||
if (__builtin_constant_p(rn) && rn < 1024) \
|
||||
asm volatile("mtdcr " __stringify(rn) ",%0" \
|
||||
: : "r" (v)); \
|
||||
asm volatile("mtdcr %0, %1" \
|
||||
: : "n" (rn), "r" (v)); \
|
||||
else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR))) \
|
||||
mtdcrx(rn, v); \
|
||||
else \
|
||||
|
||||
@ -410,7 +410,6 @@ DECLARE_INTERRUPT_HANDLER(altivec_assist_exception);
|
||||
DECLARE_INTERRUPT_HANDLER(CacheLockingException);
|
||||
DECLARE_INTERRUPT_HANDLER(SPEFloatingPointException);
|
||||
DECLARE_INTERRUPT_HANDLER(SPEFloatingPointRoundException);
|
||||
DECLARE_INTERRUPT_HANDLER(unrecoverable_exception);
|
||||
DECLARE_INTERRUPT_HANDLER(WatchdogException);
|
||||
DECLARE_INTERRUPT_HANDLER(kernel_bad_stack);
|
||||
|
||||
@ -437,6 +436,8 @@ DECLARE_INTERRUPT_HANDLER_NMI(hmi_exception_realmode);
|
||||
|
||||
DECLARE_INTERRUPT_HANDLER_ASYNC(TAUException);
|
||||
|
||||
void unrecoverable_exception(struct pt_regs *regs);
|
||||
|
||||
void replay_system_reset(void);
|
||||
void replay_soft_interrupts(void);
|
||||
|
||||
|
||||
@ -228,7 +228,7 @@ enum {
|
||||
#define MMU_FTRS_ALWAYS 0
|
||||
#endif
|
||||
|
||||
static inline bool early_mmu_has_feature(unsigned long feature)
|
||||
static __always_inline bool early_mmu_has_feature(unsigned long feature)
|
||||
{
|
||||
if (MMU_FTRS_ALWAYS & feature)
|
||||
return true;
|
||||
@ -286,7 +286,7 @@ static inline void mmu_feature_keys_init(void)
|
||||
|
||||
}
|
||||
|
||||
static inline bool mmu_has_feature(unsigned long feature)
|
||||
static __always_inline bool mmu_has_feature(unsigned long feature)
|
||||
{
|
||||
return early_mmu_has_feature(feature);
|
||||
}
|
||||
|
||||
@ -195,7 +195,7 @@ static inline void regs_set_return_value(struct pt_regs *regs, unsigned long rc)
|
||||
#define TRAP_FLAGS_MASK 0x11
|
||||
#define TRAP(regs) ((regs)->trap & ~TRAP_FLAGS_MASK)
|
||||
#define FULL_REGS(regs) (((regs)->trap & 1) == 0)
|
||||
#define SET_FULL_REGS(regs) ((regs)->trap |= 1)
|
||||
#define SET_FULL_REGS(regs) ((regs)->trap &= ~1)
|
||||
#endif
|
||||
#define CHECK_FULL_REGS(regs) BUG_ON(!FULL_REGS(regs))
|
||||
#define NV_REG_POISON 0xdeadbeefdeadbeefUL
|
||||
@ -210,7 +210,7 @@ static inline void regs_set_return_value(struct pt_regs *regs, unsigned long rc)
|
||||
#define TRAP_FLAGS_MASK 0x1F
|
||||
#define TRAP(regs) ((regs)->trap & ~TRAP_FLAGS_MASK)
|
||||
#define FULL_REGS(regs) (((regs)->trap & 1) == 0)
|
||||
#define SET_FULL_REGS(regs) ((regs)->trap |= 1)
|
||||
#define SET_FULL_REGS(regs) ((regs)->trap &= ~1)
|
||||
#define IS_CRITICAL_EXC(regs) (((regs)->trap & 2) != 0)
|
||||
#define IS_MCHECK_EXC(regs) (((regs)->trap & 4) != 0)
|
||||
#define IS_DEBUG_EXC(regs) (((regs)->trap & 8) != 0)
|
||||
|
||||
@ -71,6 +71,16 @@ static inline void disable_kernel_vsx(void)
|
||||
{
|
||||
msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
|
||||
}
|
||||
#else
|
||||
static inline void enable_kernel_vsx(void)
|
||||
{
|
||||
BUILD_BUG();
|
||||
}
|
||||
|
||||
static inline void disable_kernel_vsx(void)
|
||||
{
|
||||
BUILD_BUG();
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPE
|
||||
|
||||
@ -113,7 +113,7 @@ struct vio_driver {
|
||||
const char *name;
|
||||
const struct vio_device_id *id_table;
|
||||
int (*probe)(struct vio_dev *dev, const struct vio_device_id *id);
|
||||
int (*remove)(struct vio_dev *dev);
|
||||
void (*remove)(struct vio_dev *dev);
|
||||
/* A driver must have a get_desired_dma() function to
|
||||
* be loaded in a CMO environment if it uses DMA.
|
||||
*/
|
||||
|
||||
@ -466,7 +466,7 @@ DEFINE_FIXED_SYMBOL(\name\()_common_real)
|
||||
|
||||
ld r10,PACAKMSR(r13) /* get MSR value for kernel */
|
||||
/* MSR[RI] is clear iff using SRR regs */
|
||||
.if IHSRR == EXC_HV_OR_STD
|
||||
.if IHSRR_IF_HVMODE
|
||||
BEGIN_FTR_SECTION
|
||||
xori r10,r10,MSR_RI
|
||||
END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE)
|
||||
|
||||
@ -457,11 +457,12 @@ InstructionTLBMiss:
|
||||
cmplw 0,r1,r3
|
||||
#endif
|
||||
mfspr r2, SPRN_SDR1
|
||||
li r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
|
||||
li r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC | _PAGE_USER
|
||||
rlwinm r2, r2, 28, 0xfffff000
|
||||
#ifdef CONFIG_MODULES
|
||||
bgt- 112f
|
||||
lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
|
||||
li r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
|
||||
addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
|
||||
#endif
|
||||
112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
|
||||
@ -520,10 +521,11 @@ DataLoadTLBMiss:
|
||||
lis r1, TASK_SIZE@h /* check if kernel address */
|
||||
cmplw 0,r1,r3
|
||||
mfspr r2, SPRN_SDR1
|
||||
li r1, _PAGE_PRESENT | _PAGE_ACCESSED
|
||||
li r1, _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER
|
||||
rlwinm r2, r2, 28, 0xfffff000
|
||||
bgt- 112f
|
||||
lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
|
||||
li r1, _PAGE_PRESENT | _PAGE_ACCESSED
|
||||
addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
|
||||
112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
|
||||
lwz r2,0(r2) /* get pmd entry */
|
||||
@ -597,10 +599,11 @@ DataStoreTLBMiss:
|
||||
lis r1, TASK_SIZE@h /* check if kernel address */
|
||||
cmplw 0,r1,r3
|
||||
mfspr r2, SPRN_SDR1
|
||||
li r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT | _PAGE_ACCESSED
|
||||
li r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER
|
||||
rlwinm r2, r2, 28, 0xfffff000
|
||||
bgt- 112f
|
||||
lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
|
||||
li r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT | _PAGE_ACCESSED
|
||||
addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
|
||||
112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
|
||||
lwz r2,0(r2) /* get pmd entry */
|
||||
|
||||
@ -149,7 +149,7 @@ notrace long system_call_exception(long r3, long r4, long r5,
|
||||
* enabled when the interrupt handler returns (indicating a process-context /
|
||||
* synchronous interrupt) then irqs_enabled should be true.
|
||||
*/
|
||||
static notrace inline bool __prep_irq_for_enabled_exit(bool clear_ri)
|
||||
static notrace __always_inline bool __prep_irq_for_enabled_exit(bool clear_ri)
|
||||
{
|
||||
/* This must be done with RI=1 because tracing may touch vmaps */
|
||||
trace_hardirqs_on();
|
||||
@ -436,7 +436,6 @@ again:
|
||||
return ret;
|
||||
}
|
||||
|
||||
void unrecoverable_exception(struct pt_regs *regs);
|
||||
void preempt_schedule_irq(void);
|
||||
|
||||
notrace unsigned long interrupt_exit_kernel_prepare(struct pt_regs *regs, unsigned long msr)
|
||||
|
||||
@ -2170,7 +2170,7 @@ DEFINE_INTERRUPT_HANDLER(SPEFloatingPointRoundException)
|
||||
* in the MSR is 0. This indicates that SRR0/1 are live, and that
|
||||
* we therefore lost state by taking this exception.
|
||||
*/
|
||||
DEFINE_INTERRUPT_HANDLER(unrecoverable_exception)
|
||||
void unrecoverable_exception(struct pt_regs *regs)
|
||||
{
|
||||
pr_emerg("Unrecoverable exception %lx at %lx (msr=%lx)\n",
|
||||
regs->trap, regs->nip, regs->msr);
|
||||
|
||||
@ -904,7 +904,7 @@ static nokprobe_inline int do_vsx_load(struct instruction_op *op,
|
||||
if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
|
||||
return -EFAULT;
|
||||
|
||||
nr_vsx_regs = size / sizeof(__vector128);
|
||||
nr_vsx_regs = max(1ul, size / sizeof(__vector128));
|
||||
emulate_vsx_load(op, buf, mem, cross_endian);
|
||||
preempt_disable();
|
||||
if (reg < 32) {
|
||||
@ -951,7 +951,7 @@ static nokprobe_inline int do_vsx_store(struct instruction_op *op,
|
||||
if (!address_ok(regs, ea, size))
|
||||
return -EFAULT;
|
||||
|
||||
nr_vsx_regs = size / sizeof(__vector128);
|
||||
nr_vsx_regs = max(1ul, size / sizeof(__vector128));
|
||||
preempt_disable();
|
||||
if (reg < 32) {
|
||||
/* FP regs + extensions */
|
||||
|
||||
@ -222,7 +222,7 @@ static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs *
|
||||
if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid)
|
||||
*addrp = mfspr(SPRN_SDAR);
|
||||
|
||||
if (is_kernel_addr(mfspr(SPRN_SDAR)) && perf_allow_kernel(&event->attr) != 0)
|
||||
if (is_kernel_addr(mfspr(SPRN_SDAR)) && event->attr.exclude_kernel)
|
||||
*addrp = 0;
|
||||
}
|
||||
|
||||
@ -507,7 +507,7 @@ static void power_pmu_bhrb_read(struct perf_event *event, struct cpu_hw_events *
|
||||
* addresses, hence include a check before filtering code
|
||||
*/
|
||||
if (!(ppmu->flags & PPMU_ARCH_31) &&
|
||||
is_kernel_addr(addr) && perf_allow_kernel(&event->attr) != 0)
|
||||
is_kernel_addr(addr) && event->attr.exclude_kernel)
|
||||
continue;
|
||||
|
||||
/* Branches are read most recent first (ie. mfbhrb 0 is
|
||||
|
||||
@ -4,6 +4,7 @@
|
||||
* Copyright 2006-2007 Michael Ellerman, IBM Corp.
|
||||
*/
|
||||
|
||||
#include <linux/crash_dump.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/msi.h>
|
||||
@ -458,8 +459,28 @@ again:
|
||||
return hwirq;
|
||||
}
|
||||
|
||||
virq = irq_create_mapping_affinity(NULL, hwirq,
|
||||
entry->affinity);
|
||||
/*
|
||||
* Depending on the number of online CPUs in the original
|
||||
* kernel, it is likely for CPU #0 to be offline in a kdump
|
||||
* kernel. The associated IRQs in the affinity mappings
|
||||
* provided by irq_create_affinity_masks() are thus not
|
||||
* started by irq_startup(), as per-design for managed IRQs.
|
||||
* This can be a problem with multi-queue block devices driven
|
||||
* by blk-mq : such a non-started IRQ is very likely paired
|
||||
* with the single queue enforced by blk-mq during kdump (see
|
||||
* blk_mq_alloc_tag_set()). This causes the device to remain
|
||||
* silent and likely hangs the guest at some point.
|
||||
*
|
||||
* We don't really care for fine-grained affinity when doing
|
||||
* kdump actually : simply ignore the pre-computed affinity
|
||||
* masks in this case and let the default mask with all CPUs
|
||||
* be used when creating the IRQ mappings.
|
||||
*/
|
||||
if (is_kdump_kernel())
|
||||
virq = irq_create_mapping(NULL, hwirq);
|
||||
else
|
||||
virq = irq_create_mapping_affinity(NULL, hwirq,
|
||||
entry->affinity);
|
||||
|
||||
if (!virq) {
|
||||
pr_debug("rtas_msi: Failed mapping hwirq %d\n", hwirq);
|
||||
|
||||
@ -1261,7 +1261,6 @@ static int vio_bus_remove(struct device *dev)
|
||||
struct vio_dev *viodev = to_vio_dev(dev);
|
||||
struct vio_driver *viodrv = to_vio_driver(dev->driver);
|
||||
struct device *devptr;
|
||||
int ret = 1;
|
||||
|
||||
/*
|
||||
* Hold a reference to the device after the remove function is called
|
||||
@ -1270,13 +1269,13 @@ static int vio_bus_remove(struct device *dev)
|
||||
devptr = get_device(dev);
|
||||
|
||||
if (viodrv->remove)
|
||||
ret = viodrv->remove(viodev);
|
||||
viodrv->remove(viodev);
|
||||
|
||||
if (!ret && firmware_has_feature(FW_FEATURE_CMO))
|
||||
if (firmware_has_feature(FW_FEATURE_CMO))
|
||||
vio_cmo_bus_remove(viodev);
|
||||
|
||||
put_device(devptr);
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -275,9 +275,9 @@ CONFIG_IP_VS_DH=m
|
||||
CONFIG_IP_VS_SH=m
|
||||
CONFIG_IP_VS_SED=m
|
||||
CONFIG_IP_VS_NQ=m
|
||||
CONFIG_IP_VS_TWOS=m
|
||||
CONFIG_IP_VS_FTP=m
|
||||
CONFIG_IP_VS_PE_SIP=m
|
||||
CONFIG_NF_TABLES_IPV4=y
|
||||
CONFIG_NFT_FIB_IPV4=m
|
||||
CONFIG_NF_TABLES_ARP=y
|
||||
CONFIG_IP_NF_IPTABLES=m
|
||||
@ -298,7 +298,6 @@ CONFIG_IP_NF_SECURITY=m
|
||||
CONFIG_IP_NF_ARPTABLES=m
|
||||
CONFIG_IP_NF_ARPFILTER=m
|
||||
CONFIG_IP_NF_ARP_MANGLE=m
|
||||
CONFIG_NF_TABLES_IPV6=y
|
||||
CONFIG_NFT_FIB_IPV6=m
|
||||
CONFIG_IP6_NF_IPTABLES=m
|
||||
CONFIG_IP6_NF_MATCH_AH=m
|
||||
@ -481,7 +480,6 @@ CONFIG_NLMON=m
|
||||
# CONFIG_NET_VENDOR_AQUANTIA is not set
|
||||
# CONFIG_NET_VENDOR_ARC is not set
|
||||
# CONFIG_NET_VENDOR_ATHEROS is not set
|
||||
# CONFIG_NET_VENDOR_AURORA is not set
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_BROCADE is not set
|
||||
# CONFIG_NET_VENDOR_CADENCE is not set
|
||||
@ -581,7 +579,6 @@ CONFIG_VIRTIO_BALLOON=m
|
||||
CONFIG_VIRTIO_INPUT=y
|
||||
CONFIG_VHOST_NET=m
|
||||
CONFIG_VHOST_VSOCK=m
|
||||
# CONFIG_SURFACE_PLATFORMS is not set
|
||||
CONFIG_S390_CCW_IOMMU=y
|
||||
CONFIG_S390_AP_IOMMU=y
|
||||
CONFIG_EXT4_FS=y
|
||||
@ -635,6 +632,7 @@ CONFIG_NTFS_RW=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
CONFIG_TMPFS_INODE64=y
|
||||
CONFIG_HUGETLBFS=y
|
||||
CONFIG_CONFIGFS_FS=m
|
||||
CONFIG_ECRYPT_FS=m
|
||||
@ -714,12 +712,8 @@ CONFIG_CRYPTO_VMAC=m
|
||||
CONFIG_CRYPTO_CRC32=m
|
||||
CONFIG_CRYPTO_BLAKE2S=m
|
||||
CONFIG_CRYPTO_MICHAEL_MIC=m
|
||||
CONFIG_CRYPTO_RMD128=m
|
||||
CONFIG_CRYPTO_RMD160=m
|
||||
CONFIG_CRYPTO_RMD256=m
|
||||
CONFIG_CRYPTO_RMD320=m
|
||||
CONFIG_CRYPTO_SHA3=m
|
||||
CONFIG_CRYPTO_TGR192=m
|
||||
CONFIG_CRYPTO_WP512=m
|
||||
CONFIG_CRYPTO_AES_TI=m
|
||||
CONFIG_CRYPTO_ANUBIS=m
|
||||
@ -731,7 +725,6 @@ CONFIG_CRYPTO_CAST6=m
|
||||
CONFIG_CRYPTO_DES=m
|
||||
CONFIG_CRYPTO_FCRYPT=m
|
||||
CONFIG_CRYPTO_KHAZAD=m
|
||||
CONFIG_CRYPTO_SALSA20=m
|
||||
CONFIG_CRYPTO_SEED=m
|
||||
CONFIG_CRYPTO_SERPENT=m
|
||||
CONFIG_CRYPTO_SM4=m
|
||||
@ -796,12 +789,9 @@ CONFIG_DEBUG_OBJECTS_RCU_HEAD=y
|
||||
CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y
|
||||
CONFIG_SLUB_DEBUG_ON=y
|
||||
CONFIG_SLUB_STATS=y
|
||||
CONFIG_DEBUG_KMEMLEAK=y
|
||||
CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y
|
||||
CONFIG_DEBUG_STACK_USAGE=y
|
||||
CONFIG_DEBUG_VM=y
|
||||
CONFIG_DEBUG_VM_VMACACHE=y
|
||||
CONFIG_DEBUG_VM_RB=y
|
||||
CONFIG_DEBUG_VM_PGFLAGS=y
|
||||
CONFIG_DEBUG_MEMORY_INIT=y
|
||||
CONFIG_MEMORY_NOTIFIER_ERROR_INJECT=m
|
||||
@ -838,6 +828,7 @@ CONFIG_BPF_KPROBE_OVERRIDE=y
|
||||
CONFIG_HIST_TRIGGERS=y
|
||||
CONFIG_FTRACE_STARTUP_TEST=y
|
||||
# CONFIG_EVENT_TRACE_STARTUP_TEST is not set
|
||||
CONFIG_DEBUG_ENTRY=y
|
||||
CONFIG_NOTIFIER_ERROR_INJECTION=m
|
||||
CONFIG_NETDEV_NOTIFIER_ERROR_INJECT=m
|
||||
CONFIG_FAULT_INJECTION=y
|
||||
@ -861,4 +852,3 @@ CONFIG_PERCPU_TEST=m
|
||||
CONFIG_ATOMIC64_SELFTEST=y
|
||||
CONFIG_TEST_BITOPS=m
|
||||
CONFIG_TEST_BPF=m
|
||||
CONFIG_DEBUG_ENTRY=y
|
||||
|
||||
@ -266,9 +266,9 @@ CONFIG_IP_VS_DH=m
|
||||
CONFIG_IP_VS_SH=m
|
||||
CONFIG_IP_VS_SED=m
|
||||
CONFIG_IP_VS_NQ=m
|
||||
CONFIG_IP_VS_TWOS=m
|
||||
CONFIG_IP_VS_FTP=m
|
||||
CONFIG_IP_VS_PE_SIP=m
|
||||
CONFIG_NF_TABLES_IPV4=y
|
||||
CONFIG_NFT_FIB_IPV4=m
|
||||
CONFIG_NF_TABLES_ARP=y
|
||||
CONFIG_IP_NF_IPTABLES=m
|
||||
@ -289,7 +289,6 @@ CONFIG_IP_NF_SECURITY=m
|
||||
CONFIG_IP_NF_ARPTABLES=m
|
||||
CONFIG_IP_NF_ARPFILTER=m
|
||||
CONFIG_IP_NF_ARP_MANGLE=m
|
||||
CONFIG_NF_TABLES_IPV6=y
|
||||
CONFIG_NFT_FIB_IPV6=m
|
||||
CONFIG_IP6_NF_IPTABLES=m
|
||||
CONFIG_IP6_NF_MATCH_AH=m
|
||||
@ -473,7 +472,6 @@ CONFIG_NLMON=m
|
||||
# CONFIG_NET_VENDOR_AQUANTIA is not set
|
||||
# CONFIG_NET_VENDOR_ARC is not set
|
||||
# CONFIG_NET_VENDOR_ATHEROS is not set
|
||||
# CONFIG_NET_VENDOR_AURORA is not set
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_BROCADE is not set
|
||||
# CONFIG_NET_VENDOR_CADENCE is not set
|
||||
@ -573,7 +571,6 @@ CONFIG_VIRTIO_BALLOON=m
|
||||
CONFIG_VIRTIO_INPUT=y
|
||||
CONFIG_VHOST_NET=m
|
||||
CONFIG_VHOST_VSOCK=m
|
||||
# CONFIG_SURFACE_PLATFORMS is not set
|
||||
CONFIG_S390_CCW_IOMMU=y
|
||||
CONFIG_S390_AP_IOMMU=y
|
||||
CONFIG_EXT4_FS=y
|
||||
@ -623,6 +620,7 @@ CONFIG_NTFS_RW=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
CONFIG_TMPFS_INODE64=y
|
||||
CONFIG_HUGETLBFS=y
|
||||
CONFIG_CONFIGFS_FS=m
|
||||
CONFIG_ECRYPT_FS=m
|
||||
@ -703,12 +701,8 @@ CONFIG_CRYPTO_VMAC=m
|
||||
CONFIG_CRYPTO_CRC32=m
|
||||
CONFIG_CRYPTO_BLAKE2S=m
|
||||
CONFIG_CRYPTO_MICHAEL_MIC=m
|
||||
CONFIG_CRYPTO_RMD128=m
|
||||
CONFIG_CRYPTO_RMD160=m
|
||||
CONFIG_CRYPTO_RMD256=m
|
||||
CONFIG_CRYPTO_RMD320=m
|
||||
CONFIG_CRYPTO_SHA3=m
|
||||
CONFIG_CRYPTO_TGR192=m
|
||||
CONFIG_CRYPTO_WP512=m
|
||||
CONFIG_CRYPTO_AES_TI=m
|
||||
CONFIG_CRYPTO_ANUBIS=m
|
||||
@ -720,7 +714,6 @@ CONFIG_CRYPTO_CAST6=m
|
||||
CONFIG_CRYPTO_DES=m
|
||||
CONFIG_CRYPTO_FCRYPT=m
|
||||
CONFIG_CRYPTO_KHAZAD=m
|
||||
CONFIG_CRYPTO_SALSA20=m
|
||||
CONFIG_CRYPTO_SEED=m
|
||||
CONFIG_CRYPTO_SERPENT=m
|
||||
CONFIG_CRYPTO_SM4=m
|
||||
|
||||
@ -26,7 +26,6 @@ CONFIG_CRASH_DUMP=y
|
||||
# CONFIG_SECCOMP is not set
|
||||
# CONFIG_GCC_PLUGINS is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_IBM_PARTITION=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
# CONFIG_COMPACTION is not set
|
||||
# CONFIG_MIGRATION is not set
|
||||
@ -61,11 +60,9 @@ CONFIG_RAW_DRIVER=y
|
||||
# CONFIG_HID is not set
|
||||
# CONFIG_VIRTIO_MENU is not set
|
||||
# CONFIG_VHOST_MENU is not set
|
||||
# CONFIG_SURFACE_PLATFORMS is not set
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
# CONFIG_DNOTIFY is not set
|
||||
# CONFIG_INOTIFY_USER is not set
|
||||
CONFIG_CONFIGFS_FS=y
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
# CONFIG_NETWORK_FILESYSTEMS is not set
|
||||
CONFIG_LSM="yama,loadpin,safesetid,integrity"
|
||||
|
||||
@ -14,12 +14,12 @@
|
||||
|
||||
struct s390_idle_data {
|
||||
seqcount_t seqcount;
|
||||
unsigned long long idle_count;
|
||||
unsigned long long idle_time;
|
||||
unsigned long long clock_idle_enter;
|
||||
unsigned long long clock_idle_exit;
|
||||
unsigned long long timer_idle_enter;
|
||||
unsigned long long timer_idle_exit;
|
||||
unsigned long idle_count;
|
||||
unsigned long idle_time;
|
||||
unsigned long clock_idle_enter;
|
||||
unsigned long clock_idle_exit;
|
||||
unsigned long timer_idle_enter;
|
||||
unsigned long timer_idle_exit;
|
||||
unsigned long mt_cycles_enter[8];
|
||||
};
|
||||
|
||||
|
||||
@ -98,10 +98,10 @@ extern unsigned char ptff_function_mask[16];
|
||||
|
||||
/* Query TOD offset result */
|
||||
struct ptff_qto {
|
||||
unsigned long long physical_clock;
|
||||
unsigned long long tod_offset;
|
||||
unsigned long long logical_tod_offset;
|
||||
unsigned long long tod_epoch_difference;
|
||||
unsigned long physical_clock;
|
||||
unsigned long tod_offset;
|
||||
unsigned long logical_tod_offset;
|
||||
unsigned long tod_epoch_difference;
|
||||
} __packed;
|
||||
|
||||
static inline int ptff_query(unsigned int nr)
|
||||
@ -151,9 +151,9 @@ struct ptff_qui {
|
||||
rc; \
|
||||
})
|
||||
|
||||
static inline unsigned long long local_tick_disable(void)
|
||||
static inline unsigned long local_tick_disable(void)
|
||||
{
|
||||
unsigned long long old;
|
||||
unsigned long old;
|
||||
|
||||
old = S390_lowcore.clock_comparator;
|
||||
S390_lowcore.clock_comparator = clock_comparator_max;
|
||||
@ -161,7 +161,7 @@ static inline unsigned long long local_tick_disable(void)
|
||||
return old;
|
||||
}
|
||||
|
||||
static inline void local_tick_enable(unsigned long long comp)
|
||||
static inline void local_tick_enable(unsigned long comp)
|
||||
{
|
||||
S390_lowcore.clock_comparator = comp;
|
||||
set_clock_comparator(S390_lowcore.clock_comparator);
|
||||
@ -169,9 +169,9 @@ static inline void local_tick_enable(unsigned long long comp)
|
||||
|
||||
#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
|
||||
|
||||
typedef unsigned long long cycles_t;
|
||||
typedef unsigned long cycles_t;
|
||||
|
||||
static inline unsigned long long get_tod_clock(void)
|
||||
static inline unsigned long get_tod_clock(void)
|
||||
{
|
||||
union tod_clock clk;
|
||||
|
||||
@ -179,10 +179,10 @@ static inline unsigned long long get_tod_clock(void)
|
||||
return clk.tod;
|
||||
}
|
||||
|
||||
static inline unsigned long long get_tod_clock_fast(void)
|
||||
static inline unsigned long get_tod_clock_fast(void)
|
||||
{
|
||||
#ifdef CONFIG_HAVE_MARCH_Z9_109_FEATURES
|
||||
unsigned long long clk;
|
||||
unsigned long clk;
|
||||
|
||||
asm volatile("stckf %0" : "=Q" (clk) : : "cc");
|
||||
return clk;
|
||||
@ -208,9 +208,9 @@ extern union tod_clock tod_clock_base;
|
||||
* Therefore preemption must be disabled, otherwise the returned
|
||||
* value is not guaranteed to be monotonic.
|
||||
*/
|
||||
static inline unsigned long long get_tod_clock_monotonic(void)
|
||||
static inline unsigned long get_tod_clock_monotonic(void)
|
||||
{
|
||||
unsigned long long tod;
|
||||
unsigned long tod;
|
||||
|
||||
preempt_disable_notrace();
|
||||
tod = get_tod_clock() - tod_clock_base.tod;
|
||||
@ -237,7 +237,7 @@ static inline unsigned long long get_tod_clock_monotonic(void)
|
||||
* -> ns = (th * 125) + ((tl * 125) >> 9);
|
||||
*
|
||||
*/
|
||||
static inline unsigned long long tod_to_ns(unsigned long long todval)
|
||||
static inline unsigned long tod_to_ns(unsigned long todval)
|
||||
{
|
||||
return ((todval >> 9) * 125) + (((todval & 0x1ff) * 125) >> 9);
|
||||
}
|
||||
@ -249,10 +249,10 @@ static inline unsigned long long tod_to_ns(unsigned long long todval)
|
||||
*
|
||||
* Returns: true if a is later than b
|
||||
*/
|
||||
static inline int tod_after(unsigned long long a, unsigned long long b)
|
||||
static inline int tod_after(unsigned long a, unsigned long b)
|
||||
{
|
||||
if (MACHINE_HAS_SCC)
|
||||
return (long long) a > (long long) b;
|
||||
return (long) a > (long) b;
|
||||
return a > b;
|
||||
}
|
||||
|
||||
@ -263,10 +263,10 @@ static inline int tod_after(unsigned long long a, unsigned long long b)
|
||||
*
|
||||
* Returns: true if a is later than b
|
||||
*/
|
||||
static inline int tod_after_eq(unsigned long long a, unsigned long long b)
|
||||
static inline int tod_after_eq(unsigned long a, unsigned long b)
|
||||
{
|
||||
if (MACHINE_HAS_SCC)
|
||||
return (long long) a >= (long long) b;
|
||||
return (long) a >= (long) b;
|
||||
return a >= b;
|
||||
}
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user