dt-bindings: pinctrl: qcom: Add sc8280xp TLMM binding
The Qualcomm SC8280XP platform contains a single block of registers for the TLMM block. This provides pinconf and pinmux for 228 GPIOs, 2 UFS_RESET pins and one SDC interface. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20220308221132.1423218-1-bjorn.andersson@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Bjorn Andersson
Linus Walleij
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. SC8280XP TLMM block
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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description: |
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This binding describes the Top Level Mode Multiplexer block found in the
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SC8280XP platform.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,sc8280xp-tlmm
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reg:
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maxItems: 1
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interrupts: true
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interrupt-controller: true
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'#interrupt-cells': true
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gpio-controller: true
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gpio-reserved-ranges: true
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'#gpio-cells': true
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gpio-ranges: true
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wakeup-parent: true
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required:
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- compatible
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- reg
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additionalProperties: false
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patternProperties:
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'-state$':
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oneOf:
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- $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
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- patternProperties:
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".*":
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$ref: "#/$defs/qcom-sc8280xp-tlmm-state"
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'$defs':
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qcom-sc8280xp-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$"
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- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset, ufs1_reset ]
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minItems: 1
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maxItems: 16
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async, cci_i2c,
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cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
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cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9,
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cmu_rng, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
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ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5,
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ddr_pxi6, ddr_pxi7, dp2_hot, dp3_hot, edp0_lcd, edp1_lcd,
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edp2_lcd, edp3_lcd, edp_hot, emac0_dll, emac0_mcg0, emac0_mcg1,
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emac0_mcg2, emac0_mcg3, emac0_phy, emac0_ptp, emac1_dll0,
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emac1_dll1, emac1_mcg0, emac1_mcg1, emac1_mcg2, emac1_mcg3,
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emac1_phy, emac1_ptp, gcc_gp1, gcc_gp2, gcc_gp3, gcc_gp4,
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gcc_gp5, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s, ibi_i3c,
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jitter_bist, lpass_slimbus, mdp0_vsync0, mdp0_vsync1,
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mdp0_vsync2, mdp0_vsync3, mdp0_vsync4, mdp0_vsync5,
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mdp0_vsync6, mdp0_vsync7, mdp0_vsync8, mdp1_vsync0,
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mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4,
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mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync,
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mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s1_data0,
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mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0, mi2s2_data1,
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mi2s2_sck, mi2s2_ws, mi2s_mclk1, mi2s_mclk2, pcie2a_clkreq,
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pcie2b_clkreq, pcie3a_clkreq, pcie3b_clkreq, pcie4_clkreq,
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phase_flag, pll_bist, pll_clk, prng_rosc0, prng_rosc1,
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prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qspi, qspi_clk,
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qspi_cs, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
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qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
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qup18, qup19, qup20, qup21, qup22, qup23, rgmii_0, rgmii_1,
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sd_write, sdc40, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig,
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tgu, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,
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usb0_dp, usb0_phy, usb0_sbrx, usb0_sbtx, usb0_usb4, usb1_dp,
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usb1_phy, usb1_sbrx, usb1_sbtx, usb1_usb4, usb2phy_ac,
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vsense_trigger ]
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bias-disable: true
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bias-pull-down: true
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bias-pull-up: true
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drive-strength: true
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input-enable: true
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output-high: true
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output-low: true
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required:
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- pins
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- function
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pinctrl@f100000 {
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compatible = "qcom,sc8280xp-tlmm";
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reg = <0x0f100000 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&tlmm 0 0 230>;
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gpio-wo-subnode-state {
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pins = "gpio1";
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function = "gpio";
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};
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uart-w-subnodes-state {
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rx {
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pins = "gpio4";
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function = "qup14";
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bias-pull-up;
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};
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tx {
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pins = "gpio5";
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function = "qup14";
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bias-disable;
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};
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};
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};
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...
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