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drm/amd/display: change from panel to panel cntl

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[Why]
it doesn't represent panel specifically, it's more like the control
logic for the panel

[How]
change from panel to panel cntl to make it a bit more clear

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Anthony Koo 2020-04-08 13:31:50 -04:00 committed by Alex Deucher
parent e9e7123a66
commit d4caa72e27
16 changed files with 250 additions and 248 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
drivers/gpu/drm/amd/display/dc/core/dc_link.c
View File

@ -47,7 +47,7 @@
#include "hw/clk_mgr.h"
#include "dce/dmub_psr.h"
#include "dmub/inc/dmub_cmd_dal.h"
#include "inc/hw/panel.h"
#include "inc/hw/panel_cntl.h"
#define DC_LOGGER_INIT(logger)
@ -88,8 +88,8 @@ static void dc_link_destruct(struct dc_link *link)
if (link->ddc)
dal_ddc_service_destroy(&link->ddc);
if (link->panel)
link->panel->funcs->destroy(&link->panel);
if (link->panel_cntl)
link->panel_cntl->funcs->destroy(&link->panel_cntl);
if (link->link_enc)
link->link_enc->funcs->destroy(&link->link_enc);
@ -1359,7 +1359,7 @@ static bool dc_link_construct(struct dc_link *link,
struct ddc_service_init_data ddc_service_init_data = { { 0 } };
struct dc_context *dc_ctx = init_params->ctx;
struct encoder_init_data enc_init_data = { 0 };
struct panel_init_data panel_init_data = { 0 };
struct panel_cntl_init_data panel_cntl_init_data = { 0 };
struct integrated_info info = {{{ 0 }}};
struct dc_bios *bios = init_params->dc->ctx->dc_bios;
const struct dc_vbios_funcs *bp_funcs = bios->funcs;
@ -1461,18 +1461,18 @@ static bool dc_link_construct(struct dc_link *link,
dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
if (link->dc->res_pool->funcs->panel_create &&
if (link->dc->res_pool->funcs->panel_cntl_create &&
(link->link_id.id == CONNECTOR_ID_EDP ||
link->link_id.id == CONNECTOR_ID_LVDS)) {
panel_init_data.ctx = dc_ctx;
panel_init_data.inst = 0;
link->panel =
link->dc->res_pool->funcs->panel_create(
&panel_init_data);
panel_cntl_init_data.ctx = dc_ctx;
panel_cntl_init_data.inst = 0;
link->panel_cntl =
link->dc->res_pool->funcs->panel_cntl_create(
&panel_cntl_init_data);
if (link->panel == NULL) {
DC_ERROR("Failed to create link panel!\n");
goto panel_create_fail;
if (link->panel_cntl == NULL) {
DC_ERROR("Failed to create link panel_cntl!\n");
goto panel_cntl_create_fail;
}
}
@ -1558,9 +1558,9 @@ static bool dc_link_construct(struct dc_link *link,
device_tag_fail:
link->link_enc->funcs->destroy(&link->link_enc);
link_enc_create_fail:
if (link->panel != NULL)
link->panel->funcs->destroy(&link->panel);
panel_create_fail:
if (link->panel_cntl != NULL)
link->panel_cntl->funcs->destroy(&link->panel_cntl);
panel_cntl_create_fail:
dal_ddc_service_destroy(&link->ddc);
ddc_create_fail:
create_fail:

2
drivers/gpu/drm/amd/display/dc/dc_link.h
View File

@ -135,7 +135,7 @@ struct dc_link {
struct dc_context *ctx;
struct panel *panel;
struct panel_cntl *panel_cntl;
struct link_encoder *link_enc;
struct graphics_object_id link_id;
union ddi_channel_mapping ddi_channel_mapping;

2
drivers/gpu/drm/amd/display/dc/dce/Makefile
View File

@ -29,7 +29,7 @@
DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \
dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o \
dce_opp.o dce_dmcu.o dce_abm.o dce_ipp.o dce_aux.o \
dce_i2c.o dce_i2c_hw.o dce_i2c_sw.o dmub_psr.o dmub_abm.o dce_panel.o
dce_i2c.o dce_i2c_hw.o dce_i2c_sw.o dmub_psr.o dmub_abm.o dce_panel_cntl.o
AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))

64
drivers/gpu/drm/amd/display/dc/dce/dce_panel.c → drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
View File

@ -26,33 +26,33 @@
#include "reg_helper.h"
#include "core_types.h"
#include "dc_dmub_srv.h"
#include "panel.h"
#include "dce_panel.h"
#include "panel_cntl.h"
#include "dce_panel_cntl.h"
#define TO_DCE_PANEL(panel)\
container_of(panel, struct dce_panel, base)
#define TO_DCE_PANEL_CNTL(panel_cntl)\
container_of(panel_cntl, struct dce_panel_cntl, base)
#define CTX \
dce_panel->base.ctx
dce_panel_cntl->base.ctx
#define DC_LOGGER \
dce_panel->base.ctx->logger
dce_panel_cntl->base.ctx->logger
#define REG(reg)\
dce_panel->regs->reg
dce_panel_cntl->regs->reg
#undef FN
#define FN(reg_name, field_name) \
dce_panel->shift->field_name, dce_panel->mask->field_name
dce_panel_cntl->shift->field_name, dce_panel_cntl->mask->field_name
void dce_panel_hw_init(struct panel *panel)
void dce_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
{
}
bool dce_is_panel_backlight_on(struct panel *panel)
bool dce_is_panel_backlight_on(struct panel_cntl *panel_cntl)
{
struct dce_panel *dce_panel = TO_DCE_PANEL(panel);
struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
uint32_t value;
REG_GET(PWRSEQ_CNTL, BLON, &value);
@ -60,9 +60,9 @@ bool dce_is_panel_backlight_on(struct panel *panel)
return value;
}
bool dce_is_panel_powered_on(struct panel *panel)
bool dce_is_panel_powered_on(struct panel_cntl *panel_cntl)
{
struct dce_panel *dce_panel = TO_DCE_PANEL(panel);
struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
uint32_t pwr_seq_state, dig_on, dig_on_ovrd;
REG_GET(PWRSEQ_STATE, PWRSEQ_TARGET_STATE_R, &pwr_seq_state);
@ -72,34 +72,34 @@ bool dce_is_panel_powered_on(struct panel *panel)
return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1);
}
static void dce_panel_destroy(struct panel **panel)
static void dce_panel_cntl_destroy(struct panel_cntl **panel_cntl)
{
struct dce_panel *dce_panel = TO_DCE_PANEL(*panel);
struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(*panel_cntl);
kfree(dce_panel);
*panel = NULL;
kfree(dce_panel_cntl);
*panel_cntl = NULL;
}
static const struct panel_funcs dce_link_panel_funcs = {
.destroy = dce_panel_destroy,
.hw_init = dce_panel_hw_init,
static const struct panel_cntl_funcs dce_link_panel_cntl_funcs = {
.destroy = dce_panel_cntl_destroy,
.hw_init = dce_panel_cntl_hw_init,
.is_panel_backlight_on = dce_is_panel_backlight_on,
.is_panel_powered_on = dce_is_panel_powered_on,
};
void dce_panel_construct(
struct dce_panel *dce_panel,
const struct panel_init_data *init_data,
const struct dce_panel_registers *regs,
const struct dce_panel_shift *shift,
const struct dce_panel_mask *mask)
void dce_panel_cntl_construct(
struct dce_panel_cntl *dce_panel_cntl,
const struct panel_cntl_init_data *init_data,
const struct dce_panel_cntl_registers *regs,
const struct dce_panel_cntl_shift *shift,
const struct dce_panel_cntl_mask *mask)
{
dce_panel->regs = regs;
dce_panel->shift = shift;
dce_panel->mask = mask;
dce_panel_cntl->regs = regs;
dce_panel_cntl->shift = shift;
dce_panel_cntl->mask = mask;
dce_panel->base.funcs = &dce_link_panel_funcs;
dce_panel->base.ctx = init_data->ctx;
dce_panel->base.inst = init_data->inst;
dce_panel_cntl->base.funcs = &dce_link_panel_cntl_funcs;
dce_panel_cntl->base.ctx = init_data->ctx;
dce_panel_cntl->base.inst = init_data->inst;
}

86
drivers/gpu/drm/amd/display/dc/dce/dce_panel.h → drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
View File

@ -23,53 +23,53 @@
*
*/
#ifndef __DC_PANEL__DCE_H__
#define __DC_PANEL__DCE_H__
#ifndef __DC_PANEL_CNTL__DCE_H__
#define __DC_PANEL_CNTL__DCE_H__
#include "panel.h"
#include "panel_cntl.h"
/* set register offset with instance */
#define DCE_PANEL_SR(reg_name, block)\
#define DCE_PANEL_CNTL_SR(reg_name, block)\
.reg_name = mm ## block ## _ ## reg_name
#define DCE_PANEL_REG_LIST()\
DCE_PANEL_SR(PWRSEQ_CNTL, LVTMA), \
DCE_PANEL_SR(PWRSEQ_STATE, LVTMA), \
#define DCE_PANEL_CNTL_REG_LIST()\
DCE_PANEL_CNTL_SR(PWRSEQ_CNTL, LVTMA), \
DCE_PANEL_CNTL_SR(PWRSEQ_STATE, LVTMA), \
SR(BL_PWM_CNTL), \
SR(BL_PWM_CNTL2), \
SR(BL_PWM_PERIOD_CNTL), \
SR(BL_PWM_GRP1_REG_LOCK)
#define DCN_PANEL_SR(reg_name, block)\
#define DCN_PANEL_CNTL_SR(reg_name, block)\
.reg_name = BASE(mm ## block ## _ ## reg_name ## _BASE_IDX) + \
mm ## block ## _ ## reg_name
#define DCN_PANEL_REG_LIST()\
DCN_PANEL_SR(PWRSEQ_CNTL, LVTMA), \
DCN_PANEL_SR(PWRSEQ_STATE, LVTMA), \
#define DCN_PANEL_CNTL_REG_LIST()\
DCN_PANEL_CNTL_SR(PWRSEQ_CNTL, LVTMA), \
DCN_PANEL_CNTL_SR(PWRSEQ_STATE, LVTMA), \
SR(BL_PWM_CNTL), \
SR(BL_PWM_CNTL2), \
SR(BL_PWM_PERIOD_CNTL), \
SR(BL_PWM_GRP1_REG_LOCK)
#define DCE_PANEL_SF(block, reg_name, field_name, post_fix)\
#define DCE_PANEL_CNTL_SF(block, reg_name, field_name, post_fix)\
.field_name = block ## reg_name ## __ ## block ## field_name ## post_fix
#define DCE_PANEL_MASK_SH_LIST(mask_sh) \
DCE_PANEL_SF(LVTMA_, PWRSEQ_CNTL, BLON, mask_sh),\
DCE_PANEL_SF(LVTMA_, PWRSEQ_CNTL, DIGON, mask_sh),\
DCE_PANEL_SF(LVTMA_, PWRSEQ_CNTL, DIGON_OVRD, mask_sh),\
DCE_PANEL_SF(LVTMA_, PWRSEQ_STATE, PWRSEQ_TARGET_STATE_R, mask_sh), \
DCE_PANEL_SF(, BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \
DCE_PANEL_SF(, BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \
DCE_PANEL_SF(, BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \
DCE_PANEL_SF(, BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \
DCE_PANEL_SF(, BL_PWM_CNTL, BL_PWM_EN, mask_sh), \
DCE_PANEL_SF(, BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \
DCE_PANEL_SF(, BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \
DCE_PANEL_SF(, BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh)
#define DCE_PANEL_CNTL_MASK_SH_LIST(mask_sh) \
DCE_PANEL_CNTL_SF(LVTMA_, PWRSEQ_CNTL, BLON, mask_sh),\
DCE_PANEL_CNTL_SF(LVTMA_, PWRSEQ_CNTL, DIGON, mask_sh),\
DCE_PANEL_CNTL_SF(LVTMA_, PWRSEQ_CNTL, DIGON_OVRD, mask_sh),\
DCE_PANEL_CNTL_SF(LVTMA_, PWRSEQ_STATE, PWRSEQ_TARGET_STATE_R, mask_sh), \
DCE_PANEL_CNTL_SF(, BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \
DCE_PANEL_CNTL_SF(, BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \
DCE_PANEL_CNTL_SF(, BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \
DCE_PANEL_CNTL_SF(, BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \
DCE_PANEL_CNTL_SF(, BL_PWM_CNTL, BL_PWM_EN, mask_sh), \
DCE_PANEL_CNTL_SF(, BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \
DCE_PANEL_CNTL_SF(, BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \
DCE_PANEL_CNTL_SF(, BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh)
#define DCE_PANEL_REG_FIELD_LIST(type) \
#define DCE_PANEL_CNTL_REG_FIELD_LIST(type) \
type BLON;\
type DIGON;\
type DIGON_OVRD;\
@ -83,15 +83,15 @@
type BL_PWM_GRP1_REG_LOCK; \
type BL_PWM_GRP1_REG_UPDATE_PENDING
struct dce_panel_shift {
DCE_PANEL_REG_FIELD_LIST(uint8_t);
struct dce_panel_cntl_shift {
DCE_PANEL_CNTL_REG_FIELD_LIST(uint8_t);
};
struct dce_panel_mask {
DCE_PANEL_REG_FIELD_LIST(uint32_t);
struct dce_panel_cntl_mask {
DCE_PANEL_CNTL_REG_FIELD_LIST(uint32_t);
};
struct dce_panel_registers {
struct dce_panel_cntl_registers {
uint32_t PWRSEQ_CNTL;
uint32_t PWRSEQ_STATE;
uint32_t BL_PWM_CNTL;
@ -100,18 +100,18 @@ struct dce_panel_registers {
uint32_t BL_PWM_GRP1_REG_LOCK;
};
struct dce_panel {
struct panel base;
const struct dce_panel_registers *regs;
const struct dce_panel_shift *shift;
const struct dce_panel_mask *mask;
struct dce_panel_cntl {
struct panel_cntl base;
const struct dce_panel_cntl_registers *regs;
const struct dce_panel_cntl_shift *shift;
const struct dce_panel_cntl_mask *mask;
};
void dce_panel_construct(
struct dce_panel *panel,
const struct panel_init_data *init_data,
const struct dce_panel_registers *regs,
const struct dce_panel_shift *shift,
const struct dce_panel_mask *mask);
void dce_panel_cntl_construct(
struct dce_panel_cntl *panel_cntl,
const struct panel_cntl_init_data *init_data,
const struct dce_panel_cntl_registers *regs,
const struct dce_panel_cntl_shift *shift,
const struct dce_panel_cntl_mask *mask);
#endif /* __DC_PANEL__DCE_H__ */
#endif /* __DC_PANEL_CNTL__DCE_H__ */

34
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
View File

@ -46,7 +46,7 @@
#include "dce/dce_audio.h"
#include "dce/dce_hwseq.h"
#include "dce100/dce100_hw_sequencer.h"
#include "dce/dce_panel.h"
#include "dce/dce_panel_cntl.h"
#include "reg_helper.h"
@ -250,16 +250,16 @@ static const struct dce_stream_encoder_mask se_mask = {
SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
};
static const struct dce_panel_registers panel_regs[] = {
{ DCE_PANEL_REG_LIST() }
static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
{ DCE_PANEL_CNTL_REG_LIST() }
};
static const struct dce_panel_shift panel_shift = {
DCE_PANEL_MASK_SH_LIST(__SHIFT)
static const struct dce_panel_cntl_shift panel_cntl_shift = {
DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
};
static const struct dce_panel_mask panel_mask = {
DCE_PANEL_MASK_SH_LIST(_MASK)
static const struct dce_panel_cntl_mask panel_cntl_mask = {
DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
};
#define opp_regs(id)\
@ -640,21 +640,21 @@ struct link_encoder *dce100_link_encoder_create(
return &enc110->base;
}
static struct panel *dce100_panel_create(const struct panel_init_data *init_data)
static struct panel_cntl *dce100_panel_cntl_create(const struct panel_cntl_init_data *init_data)
{
struct dce_panel *panel =
kzalloc(sizeof(struct dce_panel), GFP_KERNEL);
struct dce_panel_cntl *panel_cntl =
kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
if (!panel)
if (!panel_cntl)
return NULL;
dce_panel_construct(panel,
dce_panel_cntl_construct(panel_cntl,
init_data,
&panel_regs[init_data->inst],
&panel_shift,
&panel_mask);
&panel_cntl_regs[init_data->inst],
&panel_cntl_shift,
&panel_cntl_mask);
return &panel->base;
return &panel_cntl->base;
}
struct output_pixel_processor *dce100_opp_create(
@ -973,7 +973,7 @@ struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link(
static const struct resource_funcs dce100_res_pool_funcs = {
.destroy = dce100_destroy_resource_pool,
.link_enc_create = dce100_link_encoder_create,
.panel_create = dce100_panel_create,
.panel_cntl_create = dce100_panel_cntl_create,
.validate_bandwidth = dce100_validate_bandwidth,
.validate_plane = dce100_validate_plane,
.add_stream_to_ctx = dce100_add_stream_to_ctx,

10
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View File

@ -53,7 +53,7 @@
#include "abm.h"
#include "audio.h"
#include "reg_helper.h"
#include "panel.h"
#include "panel_cntl.h"
/* include DCE11 register header files */
#include "dce/dce_11_0_d.h"
@ -796,10 +796,11 @@ void dce110_edp_power_control(
return;
}
if (link->panel)
if (link->panel_cntl)
return;
if (power_up != link->panel->funcs->is_panel_powered_on(link->panel)) {
if (power_up !=
link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) {
/* Send VBIOS command to prompt eDP panel power */
if (power_up) {
unsigned long long current_ts = dm_get_timestamp(ctx);
@ -878,7 +879,8 @@ void dce110_edp_backlight_control(
return;
}
if (enable && link->panel && link->panel->funcs->is_panel_backlight_on(link->panel)) {
if (enable && link->panel_cntl &&
link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl)) {
DC_LOG_HW_RESUME_S3(
"%s: panel already powered up. Do nothing.\n",
__func__);

34
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
View File

@ -53,7 +53,7 @@
#include "dce/dce_abm.h"
#include "dce/dce_dmcu.h"
#include "dce/dce_i2c.h"
#include "dce/dce_panel.h"
#include "dce/dce_panel_cntl.h"
#define DC_LOGGER \
dc->ctx->logger
@ -276,16 +276,16 @@ static const struct dce_stream_encoder_mask se_mask = {
SE_COMMON_MASK_SH_LIST_DCE110(_MASK)
};
static const struct dce_panel_registers panel_regs[] = {
{ DCE_PANEL_REG_LIST() }
static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
{ DCE_PANEL_CNTL_REG_LIST() }
};
static const struct dce_panel_shift panel_shift = {
DCE_PANEL_MASK_SH_LIST(__SHIFT)
static const struct dce_panel_cntl_shift panel_cntl_shift = {
DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
};
static const struct dce_panel_mask panel_mask = {
DCE_PANEL_MASK_SH_LIST(_MASK)
static const struct dce_panel_cntl_mask panel_cntl_mask = {
DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
};
static const struct dce110_aux_registers_shift aux_shift = {
@ -686,21 +686,21 @@ static struct link_encoder *dce110_link_encoder_create(
return &enc110->base;
}
static struct panel *dce110_panel_create(const struct panel_init_data *init_data)
static struct panel_cntl *dce110_panel_cntl_create(const struct panel_cntl_init_data *init_data)
{
struct dce_panel *panel =
kzalloc(sizeof(struct dce_panel), GFP_KERNEL);
struct dce_panel_cntl *panel_cntl =
kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
if (!panel)
if (!panel_cntl)
return NULL;
dce_panel_construct(panel,
dce_panel_cntl_construct(panel_cntl,
init_data,
&panel_regs[init_data->inst],
&panel_shift,
&panel_mask);
&panel_cntl_regs[init_data->inst],
&panel_cntl_shift,
&panel_cntl_mask);
return &panel->base;
return &panel_cntl->base;
}
static struct output_pixel_processor *dce110_opp_create(
@ -1233,7 +1233,7 @@ struct stream_encoder *dce110_find_first_free_match_stream_enc_for_link(
static const struct resource_funcs dce110_res_pool_funcs = {
.destroy = dce110_destroy_resource_pool,
.link_enc_create = dce110_link_encoder_create,
.panel_create = dce110_panel_create,
.panel_cntl_create = dce110_panel_cntl_create,
.validate_bandwidth = dce110_validate_bandwidth,
.validate_plane = dce110_validate_plane,
.acquire_idle_pipe_for_layer = dce110_acquire_underlay,

34
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
View File

@ -51,7 +51,7 @@
#include "dce/dce_dmcu.h"
#include "dce/dce_aux.h"
#include "dce/dce_i2c.h"
#include "dce/dce_panel.h"
#include "dce/dce_panel_cntl.h"
#include "reg_helper.h"
@ -239,16 +239,16 @@ static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
aux_regs(5)
};
static const struct dce_panel_registers panel_regs[] = {
{ DCE_PANEL_REG_LIST() }
static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
{ DCE_PANEL_CNTL_REG_LIST() }
};
static const struct dce_panel_shift panel_shift = {
DCE_PANEL_MASK_SH_LIST(__SHIFT)
static const struct dce_panel_cntl_shift panel_cntl_shift = {
DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
};
static const struct dce_panel_mask panel_mask = {
DCE_PANEL_MASK_SH_LIST(_MASK)
static const struct dce_panel_cntl_mask panel_cntl_mask = {
DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
};
#define hpd_regs(id)\
@ -644,21 +644,21 @@ struct link_encoder *dce112_link_encoder_create(
return &enc110->base;
}
static struct panel *dce112_panel_create(const struct panel_init_data *init_data)
static struct panel_cntl *dce112_panel_cntl_create(const struct panel_cntl_init_data *init_data)
{
struct dce_panel *panel =
kzalloc(sizeof(struct dce_panel), GFP_KERNEL);
struct dce_panel_cntl *panel_cntl =
kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
if (!panel)
if (!panel_cntl)
return NULL;
dce_panel_construct(panel,
dce_panel_cntl_construct(panel_cntl,
init_data,
&panel_regs[init_data->inst],
&panel_shift,
&panel_mask);
&panel_cntl_regs[init_data->inst],
&panel_cntl_shift,
&panel_cntl_mask);
return &panel->base;
return &panel_cntl->base;
}
static struct input_pixel_processor *dce112_ipp_create(
@ -1051,7 +1051,7 @@ static void dce112_destroy_resource_pool(struct resource_pool **pool)
static const struct resource_funcs dce112_res_pool_funcs = {
.destroy = dce112_destroy_resource_pool,
.link_enc_create = dce112_link_encoder_create,
.panel_create = dce112_panel_create,
.panel_cntl_create = dce112_panel_cntl_create,
.validate_bandwidth = dce112_validate_bandwidth,
.validate_plane = dce100_validate_plane,
.add_stream_to_ctx = dce112_add_stream_to_ctx,

34
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
View File

@ -44,7 +44,7 @@
#include "dce/dce_clock_source.h"
#include "dce/dce_ipp.h"
#include "dce/dce_mem_input.h"
#include "dce/dce_panel.h"
#include "dce/dce_panel_cntl.h"
#include "dce110/dce110_hw_sequencer.h"
#include "dce120/dce120_hw_sequencer.h"
@ -294,16 +294,16 @@ static const struct dce_stream_encoder_mask se_mask = {
SE_COMMON_MASK_SH_LIST_DCE120(_MASK)
};
static const struct dce_panel_registers panel_regs[] = {
{ DCE_PANEL_REG_LIST() }
static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
{ DCE_PANEL_CNTL_REG_LIST() }
};
static const struct dce_panel_shift panel_shift = {
DCE_PANEL_MASK_SH_LIST(__SHIFT)
static const struct dce_panel_cntl_shift panel_cntl_shift = {
DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
};
static const struct dce_panel_mask panel_mask = {
DCE_PANEL_MASK_SH_LIST(_MASK)
static const struct dce_panel_cntl_mask panel_cntl_mask = {
DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
};
static const struct dce110_aux_registers_shift aux_shift = {
@ -728,21 +728,21 @@ static struct link_encoder *dce120_link_encoder_create(
return &enc110->base;
}
static struct panel *dce120_panel_create(const struct panel_init_data *init_data)
static struct panel_cntl *dce120_panel_cntl_create(const struct panel_cntl_init_data *init_data)
{
struct dce_panel *panel =
kzalloc(sizeof(struct dce_panel), GFP_KERNEL);
struct dce_panel_cntl *panel_cntl =
kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
if (!panel)
if (!panel_cntl)
return NULL;
dce_panel_construct(panel,
dce_panel_cntl_construct(panel_cntl,
init_data,
&panel_regs[init_data->inst],
&panel_shift,
&panel_mask);
&panel_cntl_regs[init_data->inst],
&panel_cntl_shift,
&panel_cntl_mask);
return &panel->base;
return &panel_cntl->base;
}
static struct input_pixel_processor *dce120_ipp_create(
@ -910,7 +910,7 @@ static void dce120_destroy_resource_pool(struct resource_pool **pool)
static const struct resource_funcs dce120_res_pool_funcs = {
.destroy = dce120_destroy_resource_pool,
.link_enc_create = dce120_link_encoder_create,
.panel_create = dce120_panel_create,
.panel_cntl_create = dce120_panel_cntl_create,
.validate_bandwidth = dce112_validate_bandwidth,
.validate_plane = dce100_validate_plane,
.add_stream_to_ctx = dce112_add_stream_to_ctx,

34
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
View File

@ -50,7 +50,7 @@
#include "dce/dce_hwseq.h"
#include "dce80/dce80_hw_sequencer.h"
#include "dce100/dce100_resource.h"
#include "dce/dce_panel.h"
#include "dce/dce_panel_cntl.h"
#include "reg_helper.h"
@ -267,16 +267,16 @@ static const struct dce_stream_encoder_mask se_mask = {
SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
};
static const struct dce_panel_registers panel_regs[] = {
{ DCE_PANEL_REG_LIST() }
static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
{ DCE_PANEL_CNTL_REG_LIST() }
};
static const struct dce_panel_shift panel_shift = {
DCE_PANEL_MASK_SH_LIST(__SHIFT)
static const struct dce_panel_cntl_shift panel_cntl_shift = {
DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
};
static const struct dce_panel_mask panel_mask = {
DCE_PANEL_MASK_SH_LIST(_MASK)
static const struct dce_panel_cntl_mask panel_cntl_mask = {
DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
};
#define opp_regs(id)\
@ -741,21 +741,21 @@ struct link_encoder *dce80_link_encoder_create(
return &enc110->base;
}
static struct panel *dce80_panel_create(const struct panel_init_data *init_data)
static struct panel_cntl *dce80_panel_cntl_create(const struct panel_cntl_init_data *init_data)
{
struct dce_panel *panel =
kzalloc(sizeof(struct dce_panel), GFP_KERNEL);
struct dce_panel_cntl *panel_cntl =
kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
if (!panel)
if (!panel_cntl)
return NULL;
dce_panel_construct(panel,
dce_panel_cntl_construct(panel_cntl,
init_data,
&panel_regs[init_data->inst],
&panel_shift,
&panel_mask);
&panel_cntl_regs[init_data->inst],
&panel_cntl_shift,
&panel_cntl_mask);
return &panel->base;
return &panel_cntl->base;
}
struct clock_source *dce80_clock_source_create(
@ -939,7 +939,7 @@ static void dce80_destroy_resource_pool(struct resource_pool **pool)
static const struct resource_funcs dce80_res_pool_funcs = {
.destroy = dce80_destroy_resource_pool,
.link_enc_create = dce80_link_encoder_create,
.panel_create = dce80_panel_create,
.panel_cntl_create = dce80_panel_cntl_create,
.validate_bandwidth = dce80_validate_bandwidth,
.validate_plane = dce100_validate_plane,
.add_stream_to_ctx = dce100_add_stream_to_ctx,

34
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
View File

@ -51,7 +51,7 @@
#include "dce112/dce112_resource.h"
#include "dcn10_hubp.h"
#include "dcn10_hubbub.h"
#include "dce/dce_panel.h"
#include "dce/dce_panel_cntl.h"
#include "soc15_hw_ip.h"
#include "vega10_ip_offset.h"
@ -322,16 +322,16 @@ static const struct dcn10_link_enc_mask le_mask = {
LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK)
};
static const struct dce_panel_registers panel_regs[] = {
{ DCN_PANEL_REG_LIST() }
static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
{ DCN_PANEL_CNTL_REG_LIST() }
};
static const struct dce_panel_shift panel_shift = {
DCE_PANEL_MASK_SH_LIST(__SHIFT)
static const struct dce_panel_cntl_shift panel_cntl_shift = {
DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
};
static const struct dce_panel_mask panel_mask = {
DCE_PANEL_MASK_SH_LIST(_MASK)
static const struct dce_panel_cntl_mask panel_cntl_mask = {
DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
};
static const struct dce110_aux_registers_shift aux_shift = {
@ -820,21 +820,21 @@ struct link_encoder *dcn10_link_encoder_create(
return &enc10->base;
}
static struct panel *dcn10_panel_create(const struct panel_init_data *init_data)
static struct panel_cntl *dcn10_panel_cntl_create(const struct panel_cntl_init_data *init_data)
{
struct dce_panel *panel =
kzalloc(sizeof(struct dce_panel), GFP_KERNEL);
struct dce_panel_cntl *panel_cntl =
kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
if (!panel)
if (!panel_cntl)
return NULL;
dce_panel_construct(panel,
dce_panel_cntl_construct(panel_cntl,
init_data,
&panel_regs[init_data->inst],
&panel_shift,
&panel_mask);
&panel_cntl_regs[init_data->inst],
&panel_cntl_shift,
&panel_cntl_mask);
return &panel->base;
return &panel_cntl->base;
}
struct clock_source *dcn10_clock_source_create(
@ -1321,7 +1321,7 @@ static const struct dc_cap_funcs cap_funcs = {
static const struct resource_funcs dcn10_res_pool_funcs = {
.destroy = dcn10_destroy_resource_pool,
.link_enc_create = dcn10_link_encoder_create,
.panel_create = dcn10_panel_create,
.panel_cntl_create = dcn10_panel_cntl_create,
.validate_bandwidth = dcn_validate_bandwidth,
.acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer,
.validate_plane = dcn10_validate_plane,

34
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
View File

@ -61,7 +61,7 @@
#include "dcn20_dccg.h"
#include "dcn20_vmid.h"
#include "dc_link_ddc.h"
#include "dce/dce_panel.h"
#include "dce/dce_panel_cntl.h"
#include "navi10_ip_offset.h"
@ -688,16 +688,16 @@ static const struct dcn10_link_enc_mask le_mask = {
DPCS_DCN2_MASK_SH_LIST(_MASK)
};
static const struct dce_panel_registers panel_regs[] = {
{ DCN_PANEL_REG_LIST() }
static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
{ DCN_PANEL_CNTL_REG_LIST() }
};
static const struct dce_panel_shift panel_shift = {
DCE_PANEL_MASK_SH_LIST(__SHIFT)
static const struct dce_panel_cntl_shift panel_cntl_shift = {
DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
};
static const struct dce_panel_mask panel_mask = {
DCE_PANEL_MASK_SH_LIST(_MASK)
static const struct dce_panel_cntl_mask panel_cntl_mask = {
DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
};
#define ipp_regs(id)\
@ -1302,21 +1302,21 @@ struct link_encoder *dcn20_link_encoder_create(
return &enc20->enc10.base;
}
static struct panel *dcn20_panel_create(const struct panel_init_data *init_data)
static struct panel_cntl *dcn20_panel_cntl_create(const struct panel_cntl_init_data *init_data)
{
struct dce_panel *panel =
kzalloc(sizeof(struct dce_panel), GFP_KERNEL);
struct dce_panel_cntl *panel_cntl =
kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
if (!panel)
if (!panel_cntl)
return NULL;
dce_panel_construct(panel,
dce_panel_cntl_construct(panel_cntl,
init_data,
&panel_regs[init_data->inst],
&panel_shift,
&panel_mask);
&panel_cntl_regs[init_data->inst],
&panel_cntl_shift,
&panel_cntl_mask);
return &panel->base;
return &panel_cntl->base;
}
struct clock_source *dcn20_clock_source_create(
@ -3219,7 +3219,7 @@ enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_stat
static struct resource_funcs dcn20_res_pool_funcs = {
.destroy = dcn20_destroy_resource_pool,
.link_enc_create = dcn20_link_encoder_create,
.panel_create = dcn20_panel_create,
.panel_cntl_create = dcn20_panel_cntl_create,
.validate_bandwidth = dcn20_validate_bandwidth,
.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
.add_stream_to_ctx = dcn20_add_stream_to_ctx,

34
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
View File

@ -61,7 +61,7 @@
#include "dcn21_hubbub.h"
#include "dcn10/dcn10_resource.h"
#include "dce110/dce110_resource.h"
#include "dce/dce_panel.h"
#include "dce/dce_panel_cntl.h"
#include "dcn20/dcn20_dwb.h"
#include "dcn20/dcn20_mmhubbub.h"
@ -1607,16 +1607,16 @@ static const struct dcn10_link_enc_registers link_enc_regs[] = {
link_regs(4, E),
};
static const struct dce_panel_registers panel_regs[] = {
{ DCN_PANEL_REG_LIST() }
static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
{ DCN_PANEL_CNTL_REG_LIST() }
};
static const struct dce_panel_shift panel_shift = {
DCE_PANEL_MASK_SH_LIST(__SHIFT)
static const struct dce_panel_cntl_shift panel_cntl_shift = {
DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
};
static const struct dce_panel_mask panel_mask = {
DCE_PANEL_MASK_SH_LIST(_MASK)
static const struct dce_panel_cntl_mask panel_cntl_mask = {
DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
};
#define aux_regs(id)\
@ -1705,21 +1705,21 @@ static struct link_encoder *dcn21_link_encoder_create(
return &enc21->enc10.base;
}
static struct panel *dcn21_panel_create(const struct panel_init_data *init_data)
static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data)
{
struct dce_panel *panel =
kzalloc(sizeof(struct dce_panel), GFP_KERNEL);
struct dce_panel_cntl *panel_cntl =
kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
if (!panel)
if (!panel_cntl)
return NULL;
dce_panel_construct(panel,
dce_panel_cntl_construct(panel_cntl,
init_data,
&panel_regs[init_data->inst],
&panel_shift,
&panel_mask);
&panel_cntl_regs[init_data->inst],
&panel_cntl_shift,
&panel_cntl_mask);
return &panel->base;
return &panel_cntl->base;
}
#define CTX ctx
@ -1766,7 +1766,7 @@ enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_stat
static struct resource_funcs dcn21_res_pool_funcs = {
.destroy = dcn21_destroy_resource_pool,
.link_enc_create = dcn21_link_encoder_create,
.panel_create = dcn21_panel_create,
.panel_cntl_create = dcn21_panel_cntl_create,
.validate_bandwidth = dcn21_validate_bandwidth,
.populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
.add_stream_to_ctx = dcn20_add_stream_to_ctx,

6
drivers/gpu/drm/amd/display/dc/inc/core_types.h
View File

@ -38,7 +38,7 @@
#endif
#include "dwb.h"
#include "mcif_wb.h"
#include "panel.h"
#include "panel_cntl.h"
#define MAX_CLOCK_SOURCES 7
@ -93,8 +93,8 @@ struct clk_bw_params;
struct resource_funcs {
void (*destroy)(struct resource_pool **pool);
void (*link_init)(struct dc_link *link);
struct panel*(*panel_create)(
const struct panel_init_data *panel_init_data);
struct panel_cntl*(*panel_cntl_create)(
const struct panel_cntl_init_data *panel_cntl_init_data);
struct link_encoder *(*link_enc_create)(
const struct encoder_init_data *init);
bool (*validate_bandwidth)(

24
drivers/gpu/drm/amd/display/dc/inc/hw/panel.h → drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h
View File

@ -21,33 +21,33 @@
*
*/
/*
* panel.h
* panel_cntl.h
*
* Created on: Oct 6, 2015
* Author: yonsun
*/
#ifndef DC_PANEL_H_
#define DC_PANEL_H_
#ifndef DC_PANEL_CNTL_H_
#define DC_PANEL_CNTL_H_
#include "dc_types.h"
struct panel_funcs {
void (*destroy)(struct panel **panel);
void (*hw_init)(struct panel *panel);
bool (*is_panel_backlight_on)(struct panel *panel);
bool (*is_panel_powered_on)(struct panel *panel);
struct panel_cntl_funcs {
void (*destroy)(struct panel_cntl **panel_cntl);
void (*hw_init)(struct panel_cntl *panel_cntl);
bool (*is_panel_backlight_on)(struct panel_cntl *panel_cntl);
bool (*is_panel_powered_on)(struct panel_cntl *panel_cntl);
};
struct panel_init_data {
struct panel_cntl_init_data {
struct dc_context *ctx;
uint32_t inst;
};
struct panel {
const struct panel_funcs *funcs;
struct panel_cntl {
const struct panel_cntl_funcs *funcs;
struct dc_context *ctx;
uint32_t inst;
};
#endif /* DC_PANEL_H_ */
#endif /* DC_PANEL_CNTL_H_ */