ARM: DT: STi: STiH416: Add DT node for MiPHY365x
The MiPHY365x is a Generic PHY which can serve various SATA or PCIe devices. It has 2 ports which it can use for either; both SATA, both PCIe or one of each in any configuration. Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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@ -19,5 +19,15 @@
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bus-width = <8>;
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non-removable;
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};
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miphy365x_phy: miphy365x@fe382000 {
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phy_port0: port@fe382000 {
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st,sata-gen = <3>;
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};
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phy_port1: port@fe38a000 {
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st,pcie-tx-pol-inv;
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};
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};
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};
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};
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@ -37,5 +37,15 @@
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bus-width = <8>;
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non-removable;
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};
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miphy365x_phy: miphy365x@fe382000 {
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phy_port0: port@fe382000 {
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st,sata-gen = <3>;
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};
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phy_port1: port@fe38a000 {
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st,pcie-tx-pol-inv;
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};
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};
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};
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};
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@ -9,6 +9,8 @@
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#include "stih41x.dtsi"
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#include "stih416-clock.dtsi"
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#include "stih416-pinctrl.dtsi"
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#include <dt-bindings/phy/phy-miphy365x.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset-controller/stih416-resets.h>
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/ {
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@ -278,5 +280,25 @@
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clock-names = "mmc";
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clocks = <&clk_s_a1_ls 8>;
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};
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miphy365x_phy: miphy365x@fe382000 {
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compatible = "st,miphy365x-phy";
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st,syscfg = <&syscfg_rear>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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phy_port0: port@fe382000 {
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#phy-cells = <1>;
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reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
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reg-names = "sata", "pcie", "syscfg";
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};
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phy_port1: port@fe38a000 {
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#phy-cells = <1>;
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reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
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reg-names = "sata", "pcie", "syscfg";
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};
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};
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};
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};
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