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drm/i915/gvt: update misc ctl regs base on stepping info

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Misc ctl related registers are for WA purpose, should detect the
stepping info first before updating HW value.

Signed-off-by: Ping Gao <ping.a.gao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
This commit is contained in:
Ping Gao 2016-10-28 10:21:45 +08:00 committed by Zhenyu Wang
parent f24940e000
commit d4362225e8
1 changed files with 6 additions and 5 deletions
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11
drivers/gpu/drm/i915/gvt/handlers.c
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@ -1278,19 +1278,20 @@ static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset,
switch (offset) { switch (offset) {
case 0x4ddc: case 0x4ddc:
vgpu_vreg(vgpu, offset) = 0x8000003c; vgpu_vreg(vgpu, offset) = 0x8000003c;
/* WaCompressedResourceSamplerPbeMediaNewHashMode:skl */
if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER))
I915_WRITE(reg, vgpu_vreg(vgpu, offset));
break; break;
case 0x42080: case 0x42080:
vgpu_vreg(vgpu, offset) = 0x8000; vgpu_vreg(vgpu, offset) = 0x8000;
/* WaCompressedResourceDisplayNewHashMode:skl */
if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER))
I915_WRITE(reg, vgpu_vreg(vgpu, offset));
break; break;
default: default:
return -EINVAL; return -EINVAL;
} }
/**
* TODO: need detect stepping info after gvt contain such information
* 0x4ddc enabled after C0, 0x42080 enabled after E0.
*/
I915_WRITE(reg, vgpu_vreg(vgpu, offset));
return 0; return 0;
} }