From d3c84299f2088e3927bcbe36a458744a3b804d6d Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sat, 22 Feb 2020 21:54:42 +0530 Subject: [PATCH] arm64: dts: mediatek: Add I2C support for MT6797 SoC Add I2C support for Mediatek MT6797 SoC. There are a total of 8 I2C controllers in this SoC (2 being shared) and they are same as the controllers present in MT6577 SoC. Hence, the driver support is added with DT fallback method. As per the datasheet, there are controllers with _imm prefix like i2c2_imm and i2c3_imm. These appears to be in different memory regions but sharing the same pins with i2c2 and i2c3 respectively. Since there is no clear evidence of what they really are, I've adapted the numbering/naming scheme from the downstream code by Mediatek. Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20200222162444.11590-3-manivannan.sadhasivam@linaro.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6797.dtsi | 220 +++++++++++++++++++++++ 1 file changed, 220 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi index 136ef9527a0d..15fc3a194af7 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi @@ -155,6 +155,62 @@ ; }; }; + + i2c0_pins_a: i2c0 { + pins0 { + pinmux = , + ; + }; + }; + + i2c1_pins_a: i2c1 { + pins1 { + pinmux = , + ; + }; + }; + + i2c2_pins_a: i2c2 { + pins2 { + pinmux = , + ; + }; + }; + + i2c3_pins_a: i2c3 { + pins3 { + pinmux = , + ; + }; + }; + + i2c4_pins_a: i2c4 { + pins4 { + pinmux = , + ; + }; + }; + + i2c5_pins_a: i2c5 { + pins5 { + pinmux = , + ; + }; + }; + + i2c6_pins_a: i2c6 { + pins6 { + pinmux = , + ; + }; + }; + + i2c7_pins_a: i2c7 { + pins7 { + pinmux = , + ; + }; + }; }; scpsys: power-controller@10006000 { @@ -233,6 +289,170 @@ status = "disabled"; }; + i2c0: i2c@11007000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <0>; + reg = <0 0x11007000 0 0x1000>, + <0 0x11000100 0 0x80>; + interrupts = ; + clocks = <&infrasys CLK_INFRA_I2C0>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <1>; + reg = <0 0x11008000 0 0x1000>, + <0 0x11000180 0 0x80>; + interrupts = ; + clocks = <&infrasys CLK_INFRA_I2C1>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@11009000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <8>; + reg = <0 0x11009000 0 0x1000>, + <0 0x11000200 0 0x80>; + interrupts = ; + clocks = <&infrasys CLK_INFRA_I2C2>, + <&infrasys CLK_INFRA_AP_DMA>, + <&infrasys CLK_INFRA_I2C2_ARB>; + clock-names = "main", "dma", "arb"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@1100d000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <9>; + reg = <0 0x1100d000 0 0x1000>, + <0 0x11000280 0 0x80>; + interrupts = ; + clocks = <&infrasys CLK_INFRA_I2C3>, + <&infrasys CLK_INFRA_AP_DMA>, + <&infrasys CLK_INFRA_I2C3_ARB>; + clock-names = "main", "dma", "arb"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@1100e000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <6>; + reg = <0 0x1100e000 0 0x1000>, + <0 0x11000500 0 0x80>; + interrupts = ; + clocks = <&infrasys CLK_INFRA_I2C_APPM>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@11010000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <7>; + reg = <0 0x11010000 0 0x1000>, + <0 0x11000580 0 0x80>; + interrupts = ; + clocks = <&infrasys CLK_INFRA_I2C_GPUPM>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@11011000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <4>; + reg = <0 0x11011000 0 0x1000>, + <0 0x11000300 0 0x80>; + interrupts = ; + clocks = <&infrasys CLK_INFRA_I2C4>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11013000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <2>; + reg = <0 0x11013000 0 0x1000>, + <0 0x11000400 0 0x80>; + interrupts = ; + clocks = <&infrasys CLK_INFRA_I2C2_IMM>, + <&infrasys CLK_INFRA_AP_DMA>, + <&infrasys CLK_INFRA_I2C2_ARB>; + clock-names = "main", "dma", "arb"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@11014000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <3>; + reg = <0 0x11014000 0 0x1000>, + <0 0x11000480 0 0x80>; + interrupts = ; + clocks = <&infrasys CLK_INFRA_I2C3_IMM>, + <&infrasys CLK_INFRA_AP_DMA>, + <&infrasys CLK_INFRA_I2C3_ARB>; + clock-names = "main", "dma", "arb"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@1101c000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <5>; + reg = <0 0x1101c000 0 0x1000>, + <0 0x11000380 0 0x80>; + interrupts = ; + clocks = <&infrasys CLK_INFRA_I2C5>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + mmsys: mmsys_config@14000000 { compatible = "mediatek,mt6797-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>;