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MIPS: Use SLL by 0 for 32-bit truncation in `__read_64bit_c0_split'

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Optimize `__read_64bit_c0_split' and reduce the instruction count by 1,
observing that a DSLL/DSRA pair by 32, is equivalent to SLL by 0, which
architecturally truncates the value requested to 32 bits on 64-bit MIPS
hardware regardless of whether the input operand is or is not a properly
sign-extended 32-bit value.

Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
Reviewed-by: James Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17399/
Signed-off-by: James Hogan <jhogan@kernel.org>
This commit is contained in:
Maciej W. Rozycki
2017-09-29 16:26:31 +01:00
committed by James Hogan
parent b2ec33d438
commit d3a0b96818
1 changed files with 6 additions and 8 deletions
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14
arch/mips/include/asm/mipsregs.h
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@@ -1355,19 +1355,17 @@ do { \
if (sel == 0) \ if (sel == 0) \
__asm__ __volatile__( \ __asm__ __volatile__( \
".set\tmips64\n\t" \ ".set\tmips64\n\t" \
"dmfc0\t%M0, " #source "\n\t" \ "dmfc0\t%L0, " #source "\n\t" \
"dsll\t%L0, %M0, 32\n\t" \ "dsra\t%M0, %L0, 32\n\t" \
"dsra\t%M0, %M0, 32\n\t" \ "sll\t%L0, %L0, 0\n\t" \
"dsra\t%L0, %L0, 32\n\t" \
".set\tmips0" \ ".set\tmips0" \
: "=r" (__val)); \ : "=r" (__val)); \
else \ else \
__asm__ __volatile__( \ __asm__ __volatile__( \
".set\tmips64\n\t" \ ".set\tmips64\n\t" \
"dmfc0\t%M0, " #source ", " #sel "\n\t" \ "dmfc0\t%L0, " #source ", " #sel "\n\t" \
"dsll\t%L0, %M0, 32\n\t" \ "dsra\t%M0, %L0, 32\n\t" \
"dsra\t%M0, %M0, 32\n\t" \ "sll\t%L0, %L0, 0\n\t" \
"dsra\t%L0, %L0, 32\n\t" \
".set\tmips0" \ ".set\tmips0" \
: "=r" (__val)); \ : "=r" (__val)); \
local_irq_restore(__flags); \ local_irq_restore(__flags); \