forked from Minki/linux
media: hevc: Add decode params control
Add decode params control and the associated structure to group all the information that are needed to decode a reference frame as is described in ITU-T Rec. H.265 section "8.3.2 Decoding process for reference picture set". Adapt Cedrus driver to these changes. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
parent
4dd0f63b51
commit
d395a78db9
Documentation/userspace-api/media/v4l
drivers
media/v4l2-core
staging/media/sunxi/cedrus
include/media
@ -3000,9 +3000,6 @@ enum v4l2_mpeg_video_hevc_size_of_length_field -
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* - __u8
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- ``pic_struct``
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-
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* - __u8
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- ``num_active_dpb_entries``
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- The number of entries in ``dpb``.
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* - __u8
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- ``ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
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- The list of L0 reference elements as indices in the DPB.
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@ -3010,22 +3007,8 @@ enum v4l2_mpeg_video_hevc_size_of_length_field -
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- ``ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
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- The list of L1 reference elements as indices in the DPB.
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* - __u8
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- ``num_rps_poc_st_curr_before``
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- The number of reference pictures in the short-term set that come before
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the current frame.
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* - __u8
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- ``num_rps_poc_st_curr_after``
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- The number of reference pictures in the short-term set that come after
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the current frame.
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* - __u8
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- ``num_rps_poc_lt_curr``
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- The number of reference pictures in the long-term set.
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* - __u8
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- ``padding[7]``
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- ``padding``
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- Applications and drivers must set this to zero.
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* - struct :c:type:`v4l2_hevc_dpb_entry`
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- ``dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
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- The decoded picture buffer, for meta-data about reference frames.
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* - struct :c:type:`v4l2_hevc_pred_weight_table`
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- ``pred_weight_table``
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- The prediction weight coefficients for inter-picture prediction.
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@ -3281,3 +3264,78 @@ enum v4l2_mpeg_video_hevc_size_of_length_field -
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encoding the next frame queued after setting this control.
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This provides a bitmask which consists of bits [0, LTR_COUNT-1].
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This is applicable to the H264 and HEVC encoders.
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``V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS (struct)``
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Specifies various decode parameters, especially the references picture order
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count (POC) for all the lists (short, long, before, current, after) and the
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number of entries for each of them.
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These parameters are defined according to :ref:`hevc`.
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They are described in section 8.3 "Slice decoding process" of the
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specification.
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.. c:type:: v4l2_ctrl_hevc_decode_params
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.. cssclass:: longtable
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.. flat-table:: struct v4l2_ctrl_hevc_decode_params
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:header-rows: 0
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:stub-columns: 0
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:widths: 1 1 2
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* - __s32
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- ``pic_order_cnt_val``
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- PicOrderCntVal as described in section 8.3.1 "Decoding process
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for picture order count" of the specification.
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* - __u8
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- ``num_active_dpb_entries``
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- The number of entries in ``dpb``.
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* - struct :c:type:`v4l2_hevc_dpb_entry`
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- ``dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
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- The decoded picture buffer, for meta-data about reference frames.
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* - __u8
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- ``num_poc_st_curr_before``
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- The number of reference pictures in the short-term set that come before
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the current frame.
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* - __u8
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- ``num_poc_st_curr_after``
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- The number of reference pictures in the short-term set that come after
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the current frame.
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* - __u8
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- ``num_poc_lt_curr``
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- The number of reference pictures in the long-term set.
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* - __u8
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- ``poc_st_curr_before[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
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- PocStCurrBefore as described in section 8.3.2 "Decoding process for reference
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picture set.
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* - __u8
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- ``poc_st_curr_after[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
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- PocStCurrAfter as described in section 8.3.2 "Decoding process for reference
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picture set.
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* - __u8
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- ``poc_lt_curr[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
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- PocLtCurr as described in section 8.3.2 "Decoding process for reference
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picture set.
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* - __u64
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- ``flags``
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- See :ref:`Decode Parameters Flags <hevc_decode_params_flags>`
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.. _hevc_decode_params_flags:
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``Decode Parameters Flags``
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.. cssclass:: longtable
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.. flat-table::
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:header-rows: 0
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:stub-columns: 0
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:widths: 1 1 2
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* - ``V4L2_HEVC_DECODE_PARAM_FLAG_IRAP_PIC``
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- 0x00000001
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-
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* - ``V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC``
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- 0x00000002
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-
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* - ``V4L2_HEVC_DECODE_PARAM_FLAG_NO_OUTPUT_OF_PRIOR``
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- 0x00000004
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-
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@ -501,6 +501,12 @@ See also the examples in :ref:`control`.
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- n/a
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- A struct :c:type:`v4l2_ctrl_vp8_frame`, containing VP8
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frame parameters for stateless video decoders.
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* - ``V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS``
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- n/a
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- n/a
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- n/a
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- A struct :c:type:`v4l2_ctrl_hevc_decode_params`, containing HEVC
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decoding parameters for stateless video decoders.
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.. raw:: latex
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@ -337,6 +337,7 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx,
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struct v4l2_ctrl_hevc_pps *p_hevc_pps;
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struct v4l2_ctrl_hevc_slice_params *p_hevc_slice_params;
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struct v4l2_ctrl_hdr10_mastering_display *p_hdr10_mastering;
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struct v4l2_ctrl_hevc_decode_params *p_hevc_decode_params;
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struct v4l2_area *area;
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void *p = ptr.p + idx * ctrl->elem_size;
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unsigned int i;
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@ -616,23 +617,26 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx,
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zero_padding(*p_hevc_pps);
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break;
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case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS:
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p_hevc_slice_params = p;
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case V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS:
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p_hevc_decode_params = p;
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if (p_hevc_slice_params->num_active_dpb_entries >
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if (p_hevc_decode_params->num_active_dpb_entries >
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V4L2_HEVC_DPB_ENTRIES_NUM_MAX)
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return -EINVAL;
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zero_padding(p_hevc_slice_params->pred_weight_table);
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for (i = 0; i < p_hevc_slice_params->num_active_dpb_entries;
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for (i = 0; i < p_hevc_decode_params->num_active_dpb_entries;
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i++) {
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struct v4l2_hevc_dpb_entry *dpb_entry =
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&p_hevc_slice_params->dpb[i];
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&p_hevc_decode_params->dpb[i];
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zero_padding(*dpb_entry);
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}
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break;
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case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS:
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p_hevc_slice_params = p;
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zero_padding(p_hevc_slice_params->pred_weight_table);
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zero_padding(*p_hevc_slice_params);
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break;
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@ -1236,6 +1240,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl,
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case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS:
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elem_size = sizeof(struct v4l2_ctrl_hevc_slice_params);
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break;
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case V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS:
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elem_size = sizeof(struct v4l2_ctrl_hevc_decode_params);
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break;
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case V4L2_CTRL_TYPE_HDR10_CLL_INFO:
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elem_size = sizeof(struct v4l2_ctrl_hdr10_cll_info);
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break;
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@ -996,6 +996,7 @@ const char *v4l2_ctrl_get_name(u32 id)
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case V4L2_CID_MPEG_VIDEO_HEVC_SPS: return "HEVC Sequence Parameter Set";
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case V4L2_CID_MPEG_VIDEO_HEVC_PPS: return "HEVC Picture Parameter Set";
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case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: return "HEVC Slice Parameters";
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case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS: return "HEVC Decode Parameters";
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case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE: return "HEVC Decode Mode";
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case V4L2_CID_MPEG_VIDEO_HEVC_START_CODE: return "HEVC Start Code";
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@ -1487,6 +1488,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type,
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case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS:
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*type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS;
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break;
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case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS:
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*type = V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS;
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break;
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case V4L2_CID_UNIT_CELL_SIZE:
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*type = V4L2_CTRL_TYPE_AREA;
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*flags |= V4L2_CTRL_FLAG_READ_ONLY;
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@ -157,6 +157,12 @@ static const struct cedrus_control cedrus_controls[] = {
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},
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.codec = CEDRUS_CODEC_VP8,
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},
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{
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.cfg = {
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.id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS,
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},
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.codec = CEDRUS_CODEC_H265,
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},
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};
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#define CEDRUS_CONTROLS_COUNT ARRAY_SIZE(cedrus_controls)
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@ -77,6 +77,7 @@ struct cedrus_h265_run {
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const struct v4l2_ctrl_hevc_sps *sps;
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const struct v4l2_ctrl_hevc_pps *pps;
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const struct v4l2_ctrl_hevc_slice_params *slice_params;
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const struct v4l2_ctrl_hevc_decode_params *decode_params;
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};
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struct cedrus_vp8_run {
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@ -70,6 +70,8 @@ void cedrus_device_run(void *priv)
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V4L2_CID_MPEG_VIDEO_HEVC_PPS);
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run.h265.slice_params = cedrus_find_control_data(ctx,
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V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS);
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run.h265.decode_params = cedrus_find_control_data(ctx,
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V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS);
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break;
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case V4L2_PIX_FMT_VP8_FRAME:
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@ -245,6 +245,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
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const struct v4l2_ctrl_hevc_sps *sps;
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const struct v4l2_ctrl_hevc_pps *pps;
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const struct v4l2_ctrl_hevc_slice_params *slice_params;
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const struct v4l2_ctrl_hevc_decode_params *decode_params;
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const struct v4l2_hevc_pred_weight_table *pred_weight_table;
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dma_addr_t src_buf_addr;
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dma_addr_t src_buf_end_addr;
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@ -256,6 +257,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
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sps = run->h265.sps;
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pps = run->h265.pps;
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slice_params = run->h265.slice_params;
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decode_params = run->h265.decode_params;
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pred_weight_table = &slice_params->pred_weight_table;
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/* MV column buffer size and allocation. */
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@ -487,7 +489,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
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reg = VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_TC_OFFSET_DIV2(slice_params->slice_tc_offset_div2) |
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VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_BETA_OFFSET_DIV2(slice_params->slice_beta_offset_div2) |
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VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_POC_BIGEST_IN_RPS_ST(slice_params->num_rps_poc_st_curr_after == 0) |
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VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_POC_BIGEST_IN_RPS_ST(decode_params->num_poc_st_curr_after == 0) |
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VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CR_QP_OFFSET(slice_params->slice_cr_qp_offset) |
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VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CB_QP_OFFSET(slice_params->slice_cb_qp_offset) |
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VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_QP_DELTA(slice_params->slice_qp_delta);
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@ -527,8 +529,8 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
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cedrus_write(dev, VE_DEC_H265_NEIGHBOR_INFO_ADDR, reg);
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/* Write decoded picture buffer in pic list. */
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cedrus_h265_frame_info_write_dpb(ctx, slice_params->dpb,
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slice_params->num_active_dpb_entries);
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cedrus_h265_frame_info_write_dpb(ctx, decode_params->dpb,
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decode_params->num_active_dpb_entries);
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/* Output frame. */
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@ -545,7 +547,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
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/* Reference picture list 0 (for P/B frames). */
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if (slice_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) {
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cedrus_h265_ref_pic_list_write(dev, slice_params->dpb,
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cedrus_h265_ref_pic_list_write(dev, decode_params->dpb,
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slice_params->ref_idx_l0,
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slice_params->num_ref_idx_l0_active_minus1 + 1,
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VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST0);
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@ -564,7 +566,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
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/* Reference picture list 1 (for B frames). */
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if (slice_params->slice_type == V4L2_HEVC_SLICE_TYPE_B) {
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cedrus_h265_ref_pic_list_write(dev, slice_params->dpb,
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cedrus_h265_ref_pic_list_write(dev, decode_params->dpb,
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slice_params->ref_idx_l1,
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slice_params->num_ref_idx_l1_active_minus1 + 1,
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VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST1);
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@ -19,6 +19,7 @@
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#define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_CODEC_BASE + 1008)
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#define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_CODEC_BASE + 1009)
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#define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_CODEC_BASE + 1010)
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#define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS (V4L2_CID_CODEC_BASE + 1012)
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#define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_CODEC_BASE + 1015)
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#define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_CODEC_BASE + 1016)
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@ -26,6 +27,7 @@
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#define V4L2_CTRL_TYPE_HEVC_SPS 0x0120
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#define V4L2_CTRL_TYPE_HEVC_PPS 0x0121
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#define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0122
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#define V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS 0x0124
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enum v4l2_mpeg_video_hevc_decode_mode {
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V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED,
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@ -194,18 +196,10 @@ struct v4l2_ctrl_hevc_slice_params {
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__u8 pic_struct;
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/* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */
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__u8 num_active_dpb_entries;
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__u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
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__u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
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__u8 num_rps_poc_st_curr_before;
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__u8 num_rps_poc_st_curr_after;
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__u8 num_rps_poc_lt_curr;
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__u8 padding;
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/* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */
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struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
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__u8 padding[5];
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/* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */
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struct v4l2_hevc_pred_weight_table pred_weight_table;
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@ -213,4 +207,21 @@ struct v4l2_ctrl_hevc_slice_params {
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__u64 flags;
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};
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#define V4L2_HEVC_DECODE_PARAM_FLAG_IRAP_PIC 0x1
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#define V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC 0x2
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#define V4L2_HEVC_DECODE_PARAM_FLAG_NO_OUTPUT_OF_PRIOR 0x4
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struct v4l2_ctrl_hevc_decode_params {
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__s32 pic_order_cnt_val;
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__u8 num_active_dpb_entries;
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struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
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__u8 num_poc_st_curr_before;
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__u8 num_poc_st_curr_after;
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__u8 num_poc_lt_curr;
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__u8 poc_st_curr_before[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
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__u8 poc_st_curr_after[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
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__u8 poc_lt_curr[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
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__u64 flags;
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};
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#endif
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