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usb: dwc2: Update enter clock gating when port is suspended

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Updates the implementation of entering clock gating mode
when core receives port suspend.
Instead of setting the required bit fields of the registers
inline, called the "dwc2_host_enter_clock_gating()" function.

Signed-off-by: Artur Petrosyan <Arthur.Petrosyan@synopsys.com>
Link: https://lore.kernel.org/r/20210413073653.9F493A0094@mailhost.synopsys.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Artur Petrosyan 2021-04-13 11:36:52 +04:00 committed by Greg Kroah-Hartman
parent 5f9e60c061
commit d37b939cf4
1 changed files with 4 additions and 15 deletions
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19
drivers/usb/dwc2/hcd.c
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@ -3298,7 +3298,6 @@ static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
{
unsigned long flags;
u32 hprt0;
u32 pcgctl;
u32 gotgctl;
int ret = 0;
@ -3323,22 +3322,12 @@ int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
break;
case DWC2_POWER_DOWN_PARAM_HIBERNATION:
case DWC2_POWER_DOWN_PARAM_NONE:
default:
hprt0 = dwc2_read_hprt0(hsotg);
hprt0 |= HPRT0_SUSP;
dwc2_writel(hsotg, hprt0, HPRT0);
hsotg->bus_suspended = true;
/*
* If power_down is supported, Phy clock will be suspended
* after registers are backuped.
* If not hibernation nor partial power down are supported,
* clock gating is used to save power.
*/
if (!hsotg->params.power_down) {
/* Suspend the Phy Clock */
pcgctl = dwc2_readl(hsotg, PCGCTL);
pcgctl |= PCGCTL_STOPPCLK;
dwc2_writel(hsotg, pcgctl, PCGCTL);
udelay(10);
}
dwc2_host_enter_clock_gating(hsotg);
break;
}
/* For HNP the bus must be suspended for at least 200ms */