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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

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Pull perf fixes from Ingo Molnar:
 "A regression fix for a crash, and a Intel HSW uncore PMU driver fix"

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  Revert "perf/x86/intel/uncore: Move uncore_box_init() out of driver initialization"
  perf/x86/intel/uncore: Fix CBOX bit wide and UBOX reg on Haswell-EP
This commit is contained in:
Linus Torvalds 2015-06-14 14:00:13 -10:00
commit d37479aac5
3 changed files with 18 additions and 15 deletions
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9
arch/x86/kernel/cpu/perf_event_intel_uncore.c
View File

@ -839,6 +839,7 @@ static int uncore_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id
box->phys_id = phys_id; box->phys_id = phys_id;
box->pci_dev = pdev; box->pci_dev = pdev;
box->pmu = pmu; box->pmu = pmu;
uncore_box_init(box);
pci_set_drvdata(pdev, box); pci_set_drvdata(pdev, box);
raw_spin_lock(&uncore_box_lock); raw_spin_lock(&uncore_box_lock);
@ -1002,8 +1003,10 @@ static int uncore_cpu_starting(int cpu)
pmu = &type->pmus[j]; pmu = &type->pmus[j];
box = *per_cpu_ptr(pmu->box, cpu); box = *per_cpu_ptr(pmu->box, cpu);
/* called by uncore_cpu_init? */ /* called by uncore_cpu_init? */
if (box && box->phys_id >= 0) if (box && box->phys_id >= 0) {
uncore_box_init(box);
continue; continue;
}
for_each_online_cpu(k) { for_each_online_cpu(k) {
exist = *per_cpu_ptr(pmu->box, k); exist = *per_cpu_ptr(pmu->box, k);
@ -1019,8 +1022,10 @@ static int uncore_cpu_starting(int cpu)
} }
} }
if (box) if (box) {
box->phys_id = phys_id; box->phys_id = phys_id;
uncore_box_init(box);
}
} }
} }
return 0; return 0;

18
arch/x86/kernel/cpu/perf_event_intel_uncore.h
View File

@ -258,14 +258,6 @@ static inline int uncore_num_counters(struct intel_uncore_box *box)
return box->pmu->type->num_counters; return box->pmu->type->num_counters;
} }
static inline void uncore_box_init(struct intel_uncore_box *box)
{
if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
if (box->pmu->type->ops->init_box)
box->pmu->type->ops->init_box(box);
}
}
static inline void uncore_disable_box(struct intel_uncore_box *box) static inline void uncore_disable_box(struct intel_uncore_box *box)
{ {
if (box->pmu->type->ops->disable_box) if (box->pmu->type->ops->disable_box)
@ -274,8 +266,6 @@ static inline void uncore_disable_box(struct intel_uncore_box *box)
static inline void uncore_enable_box(struct intel_uncore_box *box) static inline void uncore_enable_box(struct intel_uncore_box *box)
{ {
uncore_box_init(box);
if (box->pmu->type->ops->enable_box) if (box->pmu->type->ops->enable_box)
box->pmu->type->ops->enable_box(box); box->pmu->type->ops->enable_box(box);
} }
@ -298,6 +288,14 @@ static inline u64 uncore_read_counter(struct intel_uncore_box *box,
return box->pmu->type->ops->read_counter(box, event); return box->pmu->type->ops->read_counter(box, event);
} }
static inline void uncore_box_init(struct intel_uncore_box *box)
{
if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
if (box->pmu->type->ops->init_box)
box->pmu->type->ops->init_box(box);
}
}
static inline bool uncore_box_is_fake(struct intel_uncore_box *box) static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
{ {
return (box->phys_id < 0); return (box->phys_id < 0);

6
arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
View File

@ -164,8 +164,8 @@
((1ULL << (n)) - 1))) ((1ULL << (n)) - 1)))
/* Haswell-EP Ubox */ /* Haswell-EP Ubox */
#define HSWEP_U_MSR_PMON_CTR0 0x705 #define HSWEP_U_MSR_PMON_CTR0 0x709
#define HSWEP_U_MSR_PMON_CTL0 0x709 #define HSWEP_U_MSR_PMON_CTL0 0x705
#define HSWEP_U_MSR_PMON_FILTER 0x707 #define HSWEP_U_MSR_PMON_FILTER 0x707
#define HSWEP_U_MSR_PMON_UCLK_FIXED_CTL 0x703 #define HSWEP_U_MSR_PMON_UCLK_FIXED_CTL 0x703
@ -1914,7 +1914,7 @@ static struct intel_uncore_type hswep_uncore_cbox = {
.name = "cbox", .name = "cbox",
.num_counters = 4, .num_counters = 4,
.num_boxes = 18, .num_boxes = 18,
.perf_ctr_bits = 44, .perf_ctr_bits = 48,
.event_ctl = HSWEP_C0_MSR_PMON_CTL0, .event_ctl = HSWEP_C0_MSR_PMON_CTL0,
.perf_ctr = HSWEP_C0_MSR_PMON_CTR0, .perf_ctr = HSWEP_C0_MSR_PMON_CTR0,
.event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK, .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK,