clk: mediatek: mt8183: use mtk_clk_simple_probe to simplify driver
mtk_clk_simple_probe was added by Chun-Jie to simply common flow of MediaTek clock drivers and ChenYu enhanced the error path of mtk_clk_simple_probe and added mtk_clk_simple_remove. Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other MediaTek clock drivers as well. Signed-off-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220922091841.4099-7-miles.chen@mediatek.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
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@ -34,26 +34,23 @@ static const struct mtk_gate cam_clks[] = {
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GATE_CAM(CLK_CAM_CCU, "cam_ccu", "cam_sel", 12),
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};
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static int clk_mt8183_cam_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);
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mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks),
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clk_data);
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return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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}
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static const struct mtk_clk_desc cam_desc = {
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.clks = cam_clks,
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.num_clks = ARRAY_SIZE(cam_clks),
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};
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static const struct of_device_id of_match_clk_mt8183_cam[] = {
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{ .compatible = "mediatek,mt8183-camsys", },
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{}
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{
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.compatible = "mediatek,mt8183-camsys",
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.data = &cam_desc,
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}, {
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/* sentinel */
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}
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};
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static struct platform_driver clk_mt8183_cam_drv = {
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.probe = clk_mt8183_cam_probe,
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8183-cam",
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.of_match_table = of_match_clk_mt8183_cam,
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@ -34,26 +34,23 @@ static const struct mtk_gate img_clks[] = {
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GATE_IMG(CLK_IMG_OWE, "img_owe", "img_sel", 9),
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};
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static int clk_mt8183_img_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
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mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
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clk_data);
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return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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}
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static const struct mtk_clk_desc img_desc = {
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.clks = img_clks,
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.num_clks = ARRAY_SIZE(img_clks),
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};
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static const struct of_device_id of_match_clk_mt8183_img[] = {
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{ .compatible = "mediatek,mt8183-imgsys", },
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{}
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{
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.compatible = "mediatek,mt8183-imgsys",
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.data = &img_desc,
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}, {
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/* sentinel */
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}
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};
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static struct platform_driver clk_mt8183_img_drv = {
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.probe = clk_mt8183_img_probe,
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8183-img",
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.of_match_table = of_match_clk_mt8183_img,
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@ -27,26 +27,23 @@ static const struct mtk_gate ipu_core0_clks[] = {
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GATE_IPU_CORE0(CLK_IPU_CORE0_IPU, "ipu_core0_ipu", "dsp_sel", 2),
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};
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static int clk_mt8183_ipu_core0_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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clk_data = mtk_alloc_clk_data(CLK_IPU_CORE0_NR_CLK);
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mtk_clk_register_gates(node, ipu_core0_clks, ARRAY_SIZE(ipu_core0_clks),
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clk_data);
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return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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}
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static const struct mtk_clk_desc ipu_core0_desc = {
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.clks = ipu_core0_clks,
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.num_clks = ARRAY_SIZE(ipu_core0_clks),
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};
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static const struct of_device_id of_match_clk_mt8183_ipu_core0[] = {
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{ .compatible = "mediatek,mt8183-ipu_core0", },
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{}
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{
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.compatible = "mediatek,mt8183-ipu_core0",
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.data = &ipu_core0_desc,
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}, {
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/* sentinel */
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}
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};
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static struct platform_driver clk_mt8183_ipu_core0_drv = {
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.probe = clk_mt8183_ipu_core0_probe,
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8183-ipu_core0",
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.of_match_table = of_match_clk_mt8183_ipu_core0,
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@ -27,26 +27,23 @@ static const struct mtk_gate ipu_core1_clks[] = {
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GATE_IPU_CORE1(CLK_IPU_CORE1_IPU, "ipu_core1_ipu", "dsp_sel", 2),
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};
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static int clk_mt8183_ipu_core1_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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clk_data = mtk_alloc_clk_data(CLK_IPU_CORE1_NR_CLK);
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mtk_clk_register_gates(node, ipu_core1_clks, ARRAY_SIZE(ipu_core1_clks),
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clk_data);
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return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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}
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static const struct mtk_clk_desc ipu_core1_desc = {
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.clks = ipu_core1_clks,
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.num_clks = ARRAY_SIZE(ipu_core1_clks),
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};
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static const struct of_device_id of_match_clk_mt8183_ipu_core1[] = {
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{ .compatible = "mediatek,mt8183-ipu_core1", },
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{}
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{
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.compatible = "mediatek,mt8183-ipu_core1",
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.data = &ipu_core1_desc,
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}, {
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/* sentinel */
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}
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};
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static struct platform_driver clk_mt8183_ipu_core1_drv = {
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.probe = clk_mt8183_ipu_core1_probe,
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8183-ipu_core1",
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.of_match_table = of_match_clk_mt8183_ipu_core1,
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@ -25,26 +25,23 @@ static const struct mtk_gate ipu_adl_clks[] = {
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GATE_IPU_ADL_I(CLK_IPU_ADL_CABGEN, "ipu_adl_cabgen", "dsp_sel", 24),
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};
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static int clk_mt8183_ipu_adl_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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clk_data = mtk_alloc_clk_data(CLK_IPU_ADL_NR_CLK);
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mtk_clk_register_gates(node, ipu_adl_clks, ARRAY_SIZE(ipu_adl_clks),
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clk_data);
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return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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}
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static const struct mtk_clk_desc ipu_adl_desc = {
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.clks = ipu_adl_clks,
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.num_clks = ARRAY_SIZE(ipu_adl_clks),
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};
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static const struct of_device_id of_match_clk_mt8183_ipu_adl[] = {
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{ .compatible = "mediatek,mt8183-ipu_adl", },
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{}
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{
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.compatible = "mediatek,mt8183-ipu_adl",
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.data = &ipu_adl_desc,
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}, {
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/* sentinel */
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}
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};
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static struct platform_driver clk_mt8183_ipu_adl_drv = {
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.probe = clk_mt8183_ipu_adl_probe,
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8183-ipu_adl",
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.of_match_table = of_match_clk_mt8183_ipu_adl,
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@ -94,26 +94,23 @@ static const struct mtk_gate ipu_conn_clks[] = {
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"ipu_conn_cab3to1_slice", "dsp1_sel", 17),
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};
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static int clk_mt8183_ipu_conn_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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clk_data = mtk_alloc_clk_data(CLK_IPU_CONN_NR_CLK);
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mtk_clk_register_gates(node, ipu_conn_clks, ARRAY_SIZE(ipu_conn_clks),
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clk_data);
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return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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}
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static const struct mtk_clk_desc ipu_conn_desc = {
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.clks = ipu_conn_clks,
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.num_clks = ARRAY_SIZE(ipu_conn_clks),
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};
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static const struct of_device_id of_match_clk_mt8183_ipu_conn[] = {
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{ .compatible = "mediatek,mt8183-ipu_conn", },
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{}
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{
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.compatible = "mediatek,mt8183-ipu_conn",
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.data = &ipu_conn_desc,
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}, {
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/* sentinel */
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}
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};
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static struct platform_driver clk_mt8183_ipu_conn_drv = {
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.probe = clk_mt8183_ipu_conn_probe,
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8183-ipu_conn",
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.of_match_table = of_match_clk_mt8183_ipu_conn,
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@ -26,28 +26,23 @@ static const struct mtk_gate mfg_clks[] = {
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GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0)
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};
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static int clk_mt8183_mfg_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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pm_runtime_enable(&pdev->dev);
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clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
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mtk_clk_register_gates_with_dev(node, mfg_clks, ARRAY_SIZE(mfg_clks),
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clk_data, &pdev->dev);
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return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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}
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static const struct mtk_clk_desc mfg_desc = {
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.clks = mfg_clks,
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.num_clks = ARRAY_SIZE(mfg_clks),
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};
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static const struct of_device_id of_match_clk_mt8183_mfg[] = {
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{ .compatible = "mediatek,mt8183-mfgcfg", },
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{}
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{
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.compatible = "mediatek,mt8183-mfgcfg",
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.data = &mfg_desc,
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}, {
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/* sentinel */
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}
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};
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static struct platform_driver clk_mt8183_mfg_drv = {
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.probe = clk_mt8183_mfg_probe,
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8183-mfg",
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.of_match_table = of_match_clk_mt8183_mfg,
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@ -38,26 +38,23 @@ static const struct mtk_gate vdec_clks[] = {
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GATE_VDEC1_I(CLK_VDEC_LARB1, "vdec_larb1", "mm_sel", 0),
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};
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static int clk_mt8183_vdec_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
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mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
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clk_data);
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return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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}
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static const struct mtk_clk_desc vdec_desc = {
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.clks = vdec_clks,
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.num_clks = ARRAY_SIZE(vdec_clks),
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};
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static const struct of_device_id of_match_clk_mt8183_vdec[] = {
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{ .compatible = "mediatek,mt8183-vdecsys", },
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{}
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{
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.compatible = "mediatek,mt8183-vdecsys",
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.data = &vdec_desc,
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}, {
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/* sentinel */
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}
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};
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static struct platform_driver clk_mt8183_vdec_drv = {
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.probe = clk_mt8183_vdec_probe,
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8183-vdec",
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.of_match_table = of_match_clk_mt8183_vdec,
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@ -30,26 +30,23 @@ static const struct mtk_gate venc_clks[] = {
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"mm_sel", 8),
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};
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static int clk_mt8183_venc_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
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mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
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clk_data);
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return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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}
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static const struct mtk_clk_desc venc_desc = {
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.clks = venc_clks,
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.num_clks = ARRAY_SIZE(venc_clks),
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};
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static const struct of_device_id of_match_clk_mt8183_venc[] = {
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{ .compatible = "mediatek,mt8183-vencsys", },
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{}
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{
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.compatible = "mediatek,mt8183-vencsys",
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.data = &venc_desc,
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}, {
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/* sentinel */
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}
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};
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static struct platform_driver clk_mt8183_venc_drv = {
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.probe = clk_mt8183_venc_probe,
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8183-venc",
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.of_match_table = of_match_clk_mt8183_venc,
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