Merge tag 'arc-4.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC architecture updates from Vineet Gupta: - Big Endian io accessors fix [Lada] - Spellos fixes [Adam] - Fix for DW GMAC breakage [Alexey] - Making DMA API 64-bit ready - Shutting up -Wmaybe-uninitialized noise for ARC - Other minor fixes here and there, comments update * tag 'arc-4.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (21 commits) ARCv2: ioremap: Support dynamic peripheral address space ARC: dma: reintroduce platform specific dma<->phys ARC: dma: ioremap: use phys_addr_t consistenctly in code paths ARC: dma: pass_phys() not sg_virt() to cache ops ARC: dma: non-coherent pages need V-P mapping if in HIGHMEM ARC: dma: Use struct page based page allocator helpers ARC: build: Turn off -Wmaybe-uninitialized for ARC gcc 4.8 ARC: [plat-axs10x] add Ethernet PHY description in .dts arc: use of_platform_default_populate() to populate default bus ARC: thp: unbork !CONFIG_TRANSPARENT_HUGEPAGE build arc: [plat-nsimosci*] use ezchip network driver ARCv2: LLSC: software backoff is NOT needed starting HS2.1c ARC: mm: Use virt_to_pfn() for addr >> PAGE_SHIFT pattern ARC: [plat-nsim] document ranges ARC: build: Better way to detect ISA compatible toolchain ARCv2: Allow enabling PAE40 w/o HIGHMEM ARC: [BE] readl()/writel() to work in Big Endian CPU configuration ARC: [*defconfig] No need to specify CONFIG_CROSS_COMPILE ARC: [BE] Select correct CROSS_COMPILE prefix ARC: bitops: Remove non relevant comments ...
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@@ -13,8 +13,8 @@
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#include <asm/byteorder.h>
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#include <asm/page.h>
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extern void __iomem *ioremap(unsigned long physaddr, unsigned long size);
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extern void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
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extern void __iomem *ioremap(phys_addr_t paddr, unsigned long size);
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extern void __iomem *ioremap_prot(phys_addr_t paddr, unsigned long size,
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unsigned long flags);
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static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
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{
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@@ -138,15 +138,23 @@ static inline void __raw_writel(u32 w, volatile void __iomem *addr)
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#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
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/*
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* Relaxed API for drivers which can handle any ordering themselves
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* Relaxed API for drivers which can handle barrier ordering themselves
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*
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* Also these are defined to perform little endian accesses.
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* To provide the typical device register semantics of fixed endian,
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* swap the byte order for Big Endian
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*
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* http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de
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*/
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#define readb_relaxed(c) __raw_readb(c)
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#define readw_relaxed(c) __raw_readw(c)
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#define readl_relaxed(c) __raw_readl(c)
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#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
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__raw_readw(c)); __r; })
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#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
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__raw_readl(c)); __r; })
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#define writeb_relaxed(v,c) __raw_writeb(v,c)
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#define writew_relaxed(v,c) __raw_writew(v,c)
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#define writel_relaxed(v,c) __raw_writel(v,c)
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#define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
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#define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
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#include <asm-generic/io.h>
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