forked from Minki/linux
perf/x86/intel: Clean-up/reduce PEBS code
Get rid of some pointless duplication introduced by the Haswell code. Signed-off-by: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/n/tip-8q6y4davda9aawwv5yxe7klp@git.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -188,8 +188,7 @@ struct pebs_record_hsw {
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u64 r8, r9, r10, r11;
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u64 r12, r13, r14, r15;
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u64 status, dla, dse, lat;
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u64 real_ip; /* the actual eventing ip */
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u64 tsx_tuning; /* TSX abort cycles and flags */
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u64 real_ip, tsx_tuning;
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};
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union hsw_tsx_tuning {
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@ -811,10 +810,8 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
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struct pt_regs *iregs, void *__pebs)
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{
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/*
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* We cast to pebs_record_nhm to get the load latency data
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* if extra_reg MSR_PEBS_LD_LAT_THRESHOLD used
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* We cast to the biggest PEBS record are careful not
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* to access out-of-bounds members.
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* We cast to the biggest pebs_record but are careful not to
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* unconditionally access the 'extra' entries.
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*/
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct pebs_record_hsw *pebs = __pebs;
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@ -884,12 +881,11 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
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regs.flags &= ~PERF_EFLAGS_EXACT;
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if ((event->attr.sample_type & PERF_SAMPLE_ADDR) &&
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x86_pmu.intel_cap.pebs_format >= 1)
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x86_pmu.intel_cap.pebs_format >= 1)
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data.addr = pebs->dla;
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/* Only set the TSX weight when no memory weight was requested. */
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if ((event->attr.sample_type & PERF_SAMPLE_WEIGHT) &&
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!fll &&
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if ((event->attr.sample_type & PERF_SAMPLE_WEIGHT) && !fll &&
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(x86_pmu.intel_cap.pebs_format >= 2))
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data.weight = intel_hsw_weight(pebs);
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@ -941,17 +937,34 @@ static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
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__intel_pmu_pebs_event(event, iregs, at);
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}
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static void __intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, void *at,
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void *top)
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static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct debug_store *ds = cpuc->ds;
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struct perf_event *event = NULL;
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void *at, *top;
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u64 status = 0;
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int bit;
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int bit, n;
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if (!x86_pmu.pebs_active)
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return;
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at = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
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top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
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ds->pebs_index = ds->pebs_buffer_base;
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n = (top - at) / x86_pmu.pebs_record_size;
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if (n <= 0)
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return;
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/*
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* Should not happen, we program the threshold at 1 and do not
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* set a reset value.
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*/
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WARN_ONCE(n > x86_pmu.max_pebs_events,
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"Unexpected number of pebs records %d\n", n);
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for (; at < top; at += x86_pmu.pebs_record_size) {
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struct pebs_record_nhm *p = at;
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@ -979,61 +992,6 @@ static void __intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, void *at,
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}
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}
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static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct debug_store *ds = cpuc->ds;
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struct pebs_record_nhm *at, *top;
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int n;
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if (!x86_pmu.pebs_active)
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return;
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at = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
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top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
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ds->pebs_index = ds->pebs_buffer_base;
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n = top - at;
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if (n <= 0)
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return;
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/*
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* Should not happen, we program the threshold at 1 and do not
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* set a reset value.
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*/
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WARN_ONCE(n > x86_pmu.max_pebs_events,
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"Unexpected number of pebs records %d\n", n);
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return __intel_pmu_drain_pebs_nhm(iregs, at, top);
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}
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static void intel_pmu_drain_pebs_hsw(struct pt_regs *iregs)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct debug_store *ds = cpuc->ds;
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struct pebs_record_hsw *at, *top;
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int n;
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if (!x86_pmu.pebs_active)
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return;
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at = (struct pebs_record_hsw *)(unsigned long)ds->pebs_buffer_base;
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top = (struct pebs_record_hsw *)(unsigned long)ds->pebs_index;
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n = top - at;
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if (n <= 0)
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return;
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/*
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* Should not happen, we program the threshold at 1 and do not
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* set a reset value.
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*/
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WARN_ONCE(n > x86_pmu.max_pebs_events,
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"Unexpected number of pebs records %d\n", n);
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return __intel_pmu_drain_pebs_nhm(iregs, at, top);
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}
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/*
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* BTS, PEBS probe and setup
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*/
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@ -1068,7 +1026,7 @@ void intel_ds_init(void)
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case 2:
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pr_cont("PEBS fmt2%c, ", pebs_type);
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x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
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x86_pmu.drain_pebs = intel_pmu_drain_pebs_hsw;
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x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
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break;
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default:
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