forked from Minki/linux
powerpc/powernv/sriov: Drop iov->pe_num_map[]
Currently the iov->pe_num_map[] does one of two things depending on
whether single PE mode is being used or not. When it is, this contains an
array which maps a vf_index to the corresponding PE number. When single PE
mode is not being used this contains a scalar which is the base PE for the
set of enabled VFs (for for VFn is base + n).
The array was necessary because when calling pnv_ioda_alloc_pe() there is
no guarantee that the allocated PEs would be contigious. We can now
allocate contigious blocks of PEs so this is no longer an issue. This
allows us to drop the if (single_mode) {} .. else {} block scattered
through the SR-IOV code which is a nice clean up.
This also fixes a bug in pnv_pci_sriov_disable() which is the non-atomic
bitmap_clear() to manipulate the PE allocation map. Other users of the map
assume it will be accessed with atomic ops.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200722065715.1432738-11-oohall@gmail.com
This commit is contained in:
Oliver O'Halloran
Michael Ellerman
parent
a4bc676ed5
commit
d29a2488d2
@ -452,11 +452,13 @@ static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
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if (iov->m64_single_mode) {
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int pe_num = iov->vf_pe_arr[j].pe_number;
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size = pci_iov_resource_size(pdev,
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PCI_IOV_RESOURCES + i);
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start = res->start + size * j;
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rc = pnv_ioda_map_m64_single(phb, win,
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iov->pe_num_map[j],
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pe_num,
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start,
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size);
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} else {
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@ -595,38 +597,24 @@ static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
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static void pnv_pci_sriov_disable(struct pci_dev *pdev)
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{
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u16 num_vfs, base_pe;
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struct pnv_phb *phb;
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struct pnv_ioda_pe *pe;
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struct pnv_iov_data *iov;
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u16 num_vfs, i;
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phb = pci_bus_to_pnvhb(pdev->bus);
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iov = pnv_iov_get(pdev);
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num_vfs = iov->num_vfs;
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base_pe = iov->vf_pe_arr[0].pe_number;
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/* Release VF PEs */
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pnv_ioda_release_vf_PE(pdev);
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if (phb->type == PNV_PHB_IODA2) {
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if (!iov->m64_single_mode)
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pnv_pci_vf_resource_shift(pdev, -*iov->pe_num_map);
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pnv_pci_vf_resource_shift(pdev, -base_pe);
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/* Release M64 windows */
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pnv_pci_vf_release_m64(pdev, num_vfs);
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/* Release PE numbers */
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if (iov->m64_single_mode) {
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for (i = 0; i < num_vfs; i++) {
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if (iov->pe_num_map[i] == IODA_INVALID_PE)
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continue;
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pe = &phb->ioda.pe_array[iov->pe_num_map[i]];
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pnv_ioda_free_pe(pe);
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}
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} else
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bitmap_clear(phb->ioda.pe_alloc, *iov->pe_num_map, num_vfs);
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/* Releasing pe_num_map */
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kfree(iov->pe_num_map);
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}
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}
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@ -652,13 +640,7 @@ static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
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int vf_bus = pci_iov_virtfn_bus(pdev, vf_index);
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struct pci_dn *vf_pdn;
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if (iov->m64_single_mode)
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pe_num = iov->pe_num_map[vf_index];
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else
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pe_num = *iov->pe_num_map + vf_index;
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pe = &phb->ioda.pe_array[pe_num];
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pe->pe_number = pe_num;
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pe = &iov->vf_pe_arr[vf_index];
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pe->phb = phb;
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pe->flags = PNV_IODA_PE_VF;
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pe->pbus = NULL;
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@ -666,6 +648,7 @@ static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
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pe->mve_number = -1;
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pe->rid = (vf_bus << 8) | vf_devfn;
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pe_num = pe->pe_number;
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pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
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pci_domain_nr(pdev->bus), pdev->bus->number,
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PCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num);
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@ -697,9 +680,9 @@ static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
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static int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
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{
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struct pnv_ioda_pe *base_pe;
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struct pnv_iov_data *iov;
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struct pnv_phb *phb;
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struct pnv_ioda_pe *pe;
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int ret;
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u16 i;
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@ -713,55 +696,14 @@ static int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
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return -ENOSPC;
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}
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/*
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* When M64 BARs functions in Single PE mode, the number of VFs
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* could be enabled must be less than the number of M64 BARs.
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*/
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if (iov->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
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dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
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/* allocate a contigious block of PEs for our VFs */
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base_pe = pnv_ioda_alloc_pe(phb, num_vfs);
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if (!base_pe) {
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pci_err(pdev, "Unable to allocate PEs for %d VFs\n", num_vfs);
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return -EBUSY;
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}
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/* Allocating pe_num_map */
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if (iov->m64_single_mode)
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iov->pe_num_map = kmalloc_array(num_vfs,
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sizeof(*iov->pe_num_map),
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GFP_KERNEL);
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else
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iov->pe_num_map = kmalloc(sizeof(*iov->pe_num_map), GFP_KERNEL);
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if (!iov->pe_num_map)
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return -ENOMEM;
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if (iov->m64_single_mode)
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for (i = 0; i < num_vfs; i++)
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iov->pe_num_map[i] = IODA_INVALID_PE;
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/* Calculate available PE for required VFs */
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if (iov->m64_single_mode) {
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for (i = 0; i < num_vfs; i++) {
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pe = pnv_ioda_alloc_pe(phb);
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if (!pe) {
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ret = -EBUSY;
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goto m64_failed;
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}
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iov->pe_num_map[i] = pe->pe_number;
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}
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} else {
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mutex_lock(&phb->ioda.pe_alloc_mutex);
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*iov->pe_num_map = bitmap_find_next_zero_area(
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phb->ioda.pe_alloc, phb->ioda.total_pe_num,
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0, num_vfs, 0);
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if (*iov->pe_num_map >= phb->ioda.total_pe_num) {
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mutex_unlock(&phb->ioda.pe_alloc_mutex);
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dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
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kfree(iov->pe_num_map);
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return -EBUSY;
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}
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bitmap_set(phb->ioda.pe_alloc, *iov->pe_num_map, num_vfs);
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mutex_unlock(&phb->ioda.pe_alloc_mutex);
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}
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iov->vf_pe_arr = base_pe;
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iov->num_vfs = num_vfs;
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/* Assign M64 window accordingly */
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@ -777,9 +719,10 @@ static int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
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* Otherwise, the PE# for the VF will conflict with others.
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*/
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if (!iov->m64_single_mode) {
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ret = pnv_pci_vf_resource_shift(pdev, *iov->pe_num_map);
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ret = pnv_pci_vf_resource_shift(pdev,
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base_pe->pe_number);
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if (ret)
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goto m64_failed;
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goto shift_failed;
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}
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}
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@ -788,20 +731,12 @@ static int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
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return 0;
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shift_failed:
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pnv_pci_vf_release_m64(pdev, num_vfs);
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m64_failed:
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if (iov->m64_single_mode) {
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for (i = 0; i < num_vfs; i++) {
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if (iov->pe_num_map[i] == IODA_INVALID_PE)
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continue;
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pe = &phb->ioda.pe_array[iov->pe_num_map[i]];
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pnv_ioda_free_pe(pe);
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}
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} else
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bitmap_clear(phb->ioda.pe_alloc, *iov->pe_num_map, num_vfs);
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/* Releasing pe_num_map */
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kfree(iov->pe_num_map);
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for (i = 0; i < num_vfs; i++)
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pnv_ioda_free_pe(&iov->vf_pe_arr[i]);
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return ret;
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}
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@ -239,7 +239,12 @@ struct pnv_iov_data {
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/* number of VFs enabled */
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u16 num_vfs;
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unsigned int *pe_num_map; /* PE# for the first VF PE or array */
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/*
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* Pointer to the IODA PE state of each VF. Note that this is a pointer
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* into the PHB's PE array (phb->ioda.pe_array).
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*/
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struct pnv_ioda_pe *vf_pe_arr;
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/* Did we map the VF BARs with single-PE IODA BARs? */
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bool m64_single_mode;
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