forked from Minki/linux
octeontx2-pf: cn10k: Initialise NIX context
On CN10K platform NIX RQ and SQ context structure got changed. This patch uses new mbox message "NIX_CN10K_AQ_ENQ" for NIX context initialization on CN10K platform. This patch also updates the nix_rx_parse_s and nix_sqe_sg_s structures to add packet steering bit feilds. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -764,11 +764,79 @@ static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura)
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return otx2_sync_mbox_msg(&pfvf->mbox);
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}
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static int cn10k_sq_aq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura)
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{
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struct nix_cn10k_aq_enq_req *aq;
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/* Get memory to put this msg */
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aq = otx2_mbox_alloc_msg_nix_cn10k_aq_enq(&pfvf->mbox);
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if (!aq)
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return -ENOMEM;
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aq->sq.cq = pfvf->hw.rx_queues + qidx;
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aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */
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aq->sq.cq_ena = 1;
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aq->sq.ena = 1;
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/* Only one SMQ is allocated, map all SQ's to that SMQ */
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aq->sq.smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0];
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/* FIXME: set based on NIX_AF_DWRR_RPM_MTU*/
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aq->sq.smq_rr_weight = OTX2_MAX_MTU;
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aq->sq.default_chan = pfvf->hw.tx_chan_base;
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aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */
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aq->sq.sqb_aura = sqb_aura;
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aq->sq.sq_int_ena = NIX_SQINT_BITS;
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aq->sq.qint_idx = 0;
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/* Due pipelining impact minimum 2000 unused SQ CQE's
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* need to maintain to avoid CQ overflow.
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*/
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aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt));
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/* Fill AQ info */
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aq->qidx = qidx;
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aq->ctype = NIX_AQ_CTYPE_SQ;
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aq->op = NIX_AQ_INSTOP_INIT;
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return otx2_sync_mbox_msg(&pfvf->mbox);
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}
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static int otx2_sq_aq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura)
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{
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struct nix_aq_enq_req *aq;
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/* Get memory to put this msg */
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aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
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if (!aq)
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return -ENOMEM;
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aq->sq.cq = pfvf->hw.rx_queues + qidx;
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aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */
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aq->sq.cq_ena = 1;
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aq->sq.ena = 1;
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/* Only one SMQ is allocated, map all SQ's to that SMQ */
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aq->sq.smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0];
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aq->sq.smq_rr_quantum = DFLT_RR_QTM;
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aq->sq.default_chan = pfvf->hw.tx_chan_base;
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aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */
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aq->sq.sqb_aura = sqb_aura;
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aq->sq.sq_int_ena = NIX_SQINT_BITS;
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aq->sq.qint_idx = 0;
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/* Due pipelining impact minimum 2000 unused SQ CQE's
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* need to maintain to avoid CQ overflow.
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*/
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aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt));
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/* Fill AQ info */
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aq->qidx = qidx;
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aq->ctype = NIX_AQ_CTYPE_SQ;
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aq->op = NIX_AQ_INSTOP_INIT;
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return otx2_sync_mbox_msg(&pfvf->mbox);
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}
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static int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura)
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{
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struct otx2_qset *qset = &pfvf->qset;
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struct otx2_snd_queue *sq;
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struct nix_aq_enq_req *aq;
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struct otx2_pool *pool;
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int err;
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@ -811,34 +879,11 @@ static int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura)
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sq->stats.bytes = 0;
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sq->stats.pkts = 0;
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/* Get memory to put this msg */
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aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
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if (!aq)
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return -ENOMEM;
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if (is_dev_otx2(pfvf->pdev))
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return otx2_sq_aq_init(pfvf, qidx, sqb_aura);
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else
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return cn10k_sq_aq_init(pfvf, qidx, sqb_aura);
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aq->sq.cq = pfvf->hw.rx_queues + qidx;
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aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */
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aq->sq.cq_ena = 1;
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aq->sq.ena = 1;
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/* Only one SMQ is allocated, map all SQ's to that SMQ */
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aq->sq.smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0];
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aq->sq.smq_rr_quantum = DFLT_RR_QTM;
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aq->sq.default_chan = pfvf->hw.tx_chan_base;
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aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */
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aq->sq.sqb_aura = sqb_aura;
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aq->sq.sq_int_ena = NIX_SQINT_BITS;
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aq->sq.qint_idx = 0;
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/* Due pipelining impact minimum 2000 unused SQ CQE's
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* need to maintain to avoid CQ overflow.
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*/
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aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (sq->sqe_cnt));
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/* Fill AQ info */
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aq->qidx = qidx;
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aq->ctype = NIX_AQ_CTYPE_SQ;
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aq->op = NIX_AQ_INSTOP_INIT;
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return otx2_sync_mbox_msg(&pfvf->mbox);
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}
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static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx)
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@ -142,7 +142,9 @@ struct nix_rx_parse_s {
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u64 vtag0_ptr : 8; /* W5 */
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u64 vtag1_ptr : 8;
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u64 flow_key_alg : 5;
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u64 rsvd_383_341 : 43;
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u64 rsvd_359_341 : 19;
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u64 color : 2;
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u64 rsvd_383_362 : 22;
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u64 rsvd_447_384; /* W6 */
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};
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@ -218,7 +220,8 @@ struct nix_sqe_ext_s {
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u64 vlan1_ins_tci : 16;
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u64 vlan0_ins_ena : 1;
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u64 vlan1_ins_ena : 1;
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u64 rsvd_127_114 : 14;
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u64 init_color : 2;
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u64 rsvd_127_116 : 12;
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};
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struct nix_sqe_sg_s {
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@ -237,7 +240,8 @@ struct nix_sqe_sg_s {
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/* NIX send memory subdescriptor structure */
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struct nix_sqe_mem_s {
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u64 offset : 16; /* W0 */
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u64 rsvd_52_16 : 37;
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u64 rsvd_51_16 : 36;
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u64 per_lso_seg : 1;
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u64 wmem : 1;
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u64 dsz : 2;
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u64 alg : 4;
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