forked from Minki/linux
parisc/unaligned: Use EFAULT fixup handler in unaligned handlers
Convert the inline assembly code to use the automatic EFAULT exception handler. With that the fixup code can be dropped. The other change is to allow double-word only when a 64-bit kernel is used instead of depending on CONFIG_PA20. Signed-off-by: Helge Deller <deller@gmx.de>
This commit is contained in:
Helge Deller
parent
8278cc1626
commit
d1434e03b2
@ -31,13 +31,6 @@
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#define RFMT "%08lx"
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#endif
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#define FIXUP_BRANCH(lbl) \
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"\tldil L%%" #lbl ", %%r1\n" \
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"\tldo R%%" #lbl "(%%r1), %%r1\n" \
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"\tbv,n %%r0(%%r1)\n"
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/* If you use FIXUP_BRANCH, then you must list this clobber */
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#define FIXUP_BRANCH_CLOBBER "r1"
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/* 1111 1100 0000 0000 0001 0011 1100 0000 */
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#define OPCODE1(a,b,c) ((a)<<26|(b)<<12|(c)<<6)
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#define OPCODE2(a,b) ((a)<<26|(b)<<1)
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@ -114,7 +107,6 @@
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#define IM14(i) IM((i),14)
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#define ERR_NOTHANDLED -1
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#define ERR_PAGEFAULT -2
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int unaligned_enabled __read_mostly = 1;
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@ -122,7 +114,7 @@ static int emulate_ldh(struct pt_regs *regs, int toreg)
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{
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unsigned long saddr = regs->ior;
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unsigned long val = 0;
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int ret;
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ASM_EXCEPTIONTABLE_VAR(ret);
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DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n",
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regs->isr, regs->ior, toreg);
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@ -132,17 +124,12 @@ static int emulate_ldh(struct pt_regs *regs, int toreg)
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"1: ldbs 0(%%sr1,%3), %%r20\n"
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"2: ldbs 1(%%sr1,%3), %0\n"
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" depw %%r20, 23, 24, %0\n"
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" copy %%r0, %1\n"
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"3: \n"
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" .section .fixup,\"ax\"\n"
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"4: ldi -2, %1\n"
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FIXUP_BRANCH(3b)
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" .previous\n"
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ASM_EXCEPTIONTABLE_ENTRY(1b, 4b)
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ASM_EXCEPTIONTABLE_ENTRY(2b, 4b)
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: "=r" (val), "=r" (ret)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)
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: "=r" (val), "+r" (ret)
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: "0" (val), "r" (saddr), "r" (regs->isr)
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: "r20", FIXUP_BRANCH_CLOBBER );
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: "r20" );
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DPRINTF("val = 0x" RFMT "\n", val);
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@ -156,7 +143,7 @@ static int emulate_ldw(struct pt_regs *regs, int toreg, int flop)
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{
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unsigned long saddr = regs->ior;
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unsigned long val = 0;
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int ret;
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ASM_EXCEPTIONTABLE_VAR(ret);
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DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n",
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regs->isr, regs->ior, toreg);
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@ -170,17 +157,12 @@ static int emulate_ldw(struct pt_regs *regs, int toreg, int flop)
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" subi 32,%%r19,%%r19\n"
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" mtctl %%r19,11\n"
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" vshd %0,%%r20,%0\n"
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" copy %%r0, %1\n"
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"3: \n"
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" .section .fixup,\"ax\"\n"
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"4: ldi -2, %1\n"
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FIXUP_BRANCH(3b)
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" .previous\n"
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ASM_EXCEPTIONTABLE_ENTRY(1b, 4b)
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ASM_EXCEPTIONTABLE_ENTRY(2b, 4b)
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: "=r" (val), "=r" (ret)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)
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: "=r" (val), "+r" (ret)
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: "0" (val), "r" (saddr), "r" (regs->isr)
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: "r19", "r20", FIXUP_BRANCH_CLOBBER );
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: "r19", "r20" );
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DPRINTF("val = 0x" RFMT "\n", val);
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@ -195,16 +177,15 @@ static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
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{
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unsigned long saddr = regs->ior;
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__u64 val = 0;
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int ret;
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ASM_EXCEPTIONTABLE_VAR(ret);
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DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n",
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regs->isr, regs->ior, toreg);
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#ifdef CONFIG_PA20
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#ifndef CONFIG_64BIT
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if (!flop)
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return -1;
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#endif
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if (!IS_ENABLED(CONFIG_64BIT) && !flop)
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return ERR_NOTHANDLED;
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#ifdef CONFIG_64BIT
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__asm__ __volatile__ (
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" depd,z %3,60,3,%%r19\n" /* r19=(ofs&7)*8 */
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" mtsp %4, %%sr1\n"
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@ -214,17 +195,12 @@ static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
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" subi 64,%%r19,%%r19\n"
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" mtsar %%r19\n"
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" shrpd %0,%%r20,%%sar,%0\n"
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" copy %%r0, %1\n"
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"3: \n"
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" .section .fixup,\"ax\"\n"
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"4: ldi -2, %1\n"
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FIXUP_BRANCH(3b)
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" .previous\n"
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ASM_EXCEPTIONTABLE_ENTRY(1b,4b)
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ASM_EXCEPTIONTABLE_ENTRY(2b,4b)
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: "=r" (val), "=r" (ret)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)
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: "=r" (val), "+r" (ret)
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: "0" (val), "r" (saddr), "r" (regs->isr)
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: "r19", "r20", FIXUP_BRANCH_CLOBBER );
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: "r19", "r20" );
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#else
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{
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unsigned long valh=0,vall=0;
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@ -239,18 +215,13 @@ static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
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" mtsar %%r19\n"
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" vshd %0,%1,%0\n"
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" vshd %1,%%r20,%1\n"
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" copy %%r0, %2\n"
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"4: \n"
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" .section .fixup,\"ax\"\n"
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"5: ldi -2, %2\n"
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FIXUP_BRANCH(4b)
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" .previous\n"
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ASM_EXCEPTIONTABLE_ENTRY(1b,5b)
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ASM_EXCEPTIONTABLE_ENTRY(2b,5b)
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ASM_EXCEPTIONTABLE_ENTRY(3b,5b)
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: "=r" (valh), "=r" (vall), "=r" (ret)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 4b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 4b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 4b)
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: "=r" (valh), "=r" (vall), "+r" (ret)
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: "0" (valh), "1" (vall), "r" (saddr), "r" (regs->isr)
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: "r19", "r20", FIXUP_BRANCH_CLOBBER );
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: "r19", "r20" );
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val=((__u64)valh<<32)|(__u64)vall;
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}
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#endif
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@ -268,7 +239,7 @@ static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
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static int emulate_sth(struct pt_regs *regs, int frreg)
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{
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unsigned long val = regs->gr[frreg];
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int ret;
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ASM_EXCEPTIONTABLE_VAR(ret);
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if (!frreg)
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val = 0;
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@ -281,17 +252,12 @@ static int emulate_sth(struct pt_regs *regs, int frreg)
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" extrw,u %1, 23, 8, %%r19\n"
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"1: stb %1, 1(%%sr1, %2)\n"
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"2: stb %%r19, 0(%%sr1, %2)\n"
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" copy %%r0, %0\n"
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"3: \n"
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" .section .fixup,\"ax\"\n"
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"4: ldi -2, %0\n"
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FIXUP_BRANCH(3b)
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" .previous\n"
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ASM_EXCEPTIONTABLE_ENTRY(1b,4b)
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ASM_EXCEPTIONTABLE_ENTRY(2b,4b)
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: "=r" (ret)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)
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: "+r" (ret)
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: "r" (val), "r" (regs->ior), "r" (regs->isr)
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: "r19", FIXUP_BRANCH_CLOBBER );
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: "r19" );
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return ret;
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}
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@ -299,7 +265,7 @@ static int emulate_sth(struct pt_regs *regs, int frreg)
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static int emulate_stw(struct pt_regs *regs, int frreg, int flop)
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{
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unsigned long val;
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int ret;
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ASM_EXCEPTIONTABLE_VAR(ret);
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if (flop)
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val = ((__u32*)(regs->fr))[frreg];
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@ -328,24 +294,19 @@ static int emulate_stw(struct pt_regs *regs, int frreg, int flop)
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" or %%r1, %%r21, %%r21\n"
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" stw %%r20,0(%%sr1,%2)\n"
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" stw %%r21,4(%%sr1,%2)\n"
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" copy %%r0, %0\n"
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"3: \n"
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" .section .fixup,\"ax\"\n"
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"4: ldi -2, %0\n"
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FIXUP_BRANCH(3b)
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" .previous\n"
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ASM_EXCEPTIONTABLE_ENTRY(1b,4b)
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ASM_EXCEPTIONTABLE_ENTRY(2b,4b)
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: "=r" (ret)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)
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: "+r" (ret)
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: "r" (val), "r" (regs->ior), "r" (regs->isr)
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: "r19", "r20", "r21", "r22", "r1", FIXUP_BRANCH_CLOBBER );
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: "r19", "r20", "r21", "r22", "r1" );
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return ret;
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}
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static int emulate_std(struct pt_regs *regs, int frreg, int flop)
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{
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__u64 val;
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int ret;
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ASM_EXCEPTIONTABLE_VAR(ret);
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if (flop)
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val = regs->fr[frreg];
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@ -357,11 +318,10 @@ static int emulate_std(struct pt_regs *regs, int frreg, int flop)
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DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg,
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val, regs->isr, regs->ior);
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#ifdef CONFIG_PA20
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#ifndef CONFIG_64BIT
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if (!flop)
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return -1;
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#endif
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if (!IS_ENABLED(CONFIG_64BIT) && !flop)
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return ERR_NOTHANDLED;
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#ifdef CONFIG_64BIT
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__asm__ __volatile__ (
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" mtsp %3, %%sr1\n"
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" depd,z %2, 60, 3, %%r19\n"
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@ -378,19 +338,14 @@ static int emulate_std(struct pt_regs *regs, int frreg, int flop)
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" or %%r1, %%r21, %%r21\n"
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"3: std %%r20,0(%%sr1,%2)\n"
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"4: std %%r21,8(%%sr1,%2)\n"
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" copy %%r0, %0\n"
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"5: \n"
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" .section .fixup,\"ax\"\n"
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"6: ldi -2, %0\n"
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FIXUP_BRANCH(5b)
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" .previous\n"
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ASM_EXCEPTIONTABLE_ENTRY(1b,6b)
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ASM_EXCEPTIONTABLE_ENTRY(2b,6b)
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ASM_EXCEPTIONTABLE_ENTRY(3b,6b)
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ASM_EXCEPTIONTABLE_ENTRY(4b,6b)
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: "=r" (ret)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 5b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 5b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 5b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 5b)
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: "+r" (ret)
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: "r" (val), "r" (regs->ior), "r" (regs->isr)
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: "r19", "r20", "r21", "r22", "r1", FIXUP_BRANCH_CLOBBER );
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: "r19", "r20", "r21", "r22", "r1" );
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#else
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{
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unsigned long valh=(val>>32),vall=(val&0xffffffffl);
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@ -412,20 +367,15 @@ static int emulate_std(struct pt_regs *regs, int frreg, int flop)
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"3: stw %1,0(%%sr1,%3)\n"
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"4: stw %%r1,4(%%sr1,%3)\n"
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"5: stw %2,8(%%sr1,%3)\n"
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" copy %%r0, %0\n"
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"6: \n"
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" .section .fixup,\"ax\"\n"
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"7: ldi -2, %0\n"
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FIXUP_BRANCH(6b)
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" .previous\n"
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ASM_EXCEPTIONTABLE_ENTRY(1b,7b)
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ASM_EXCEPTIONTABLE_ENTRY(2b,7b)
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ASM_EXCEPTIONTABLE_ENTRY(3b,7b)
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ASM_EXCEPTIONTABLE_ENTRY(4b,7b)
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ASM_EXCEPTIONTABLE_ENTRY(5b,7b)
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: "=r" (ret)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 6b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 6b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 6b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 6b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(5b, 6b)
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: "+r" (ret)
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: "r" (valh), "r" (vall), "r" (regs->ior), "r" (regs->isr)
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: "r19", "r20", "r21", "r1", FIXUP_BRANCH_CLOBBER );
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: "r19", "r20", "r21", "r1" );
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}
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#endif
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@ -547,7 +497,7 @@ void handle_unaligned(struct pt_regs *regs)
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ret = emulate_stw(regs, R2(regs->iir),0);
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break;
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#ifdef CONFIG_PA20
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#ifdef CONFIG_64BIT
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case OPCODE_LDD_I:
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case OPCODE_LDDA_I:
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case OPCODE_LDD_S:
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@ -606,7 +556,7 @@ void handle_unaligned(struct pt_regs *regs)
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flop=1;
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ret = emulate_std(regs, R2(regs->iir),1);
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break;
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#ifdef CONFIG_PA20
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#ifdef CONFIG_64BIT
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case OPCODE_LDD_L:
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ret = emulate_ldd(regs, R2(regs->iir),0);
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break;
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@ -673,7 +623,7 @@ void handle_unaligned(struct pt_regs *regs)
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printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret);
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die_if_kernel("Unaligned data reference", regs, 28);
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if (ret == ERR_PAGEFAULT)
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if (ret == -EFAULT)
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{
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force_sig_fault(SIGSEGV, SEGV_MAPERR,
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(void __user *)regs->ior);
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