forked from Minki/linux
powerpc/64: Fix update forms of loads and stores to write 64-bit EA
When a 64-bit processor is executing in 32-bit mode, the update forms of load and store instructions are required by the architecture to write the full 64-bit effective address into the RA register, though only the bottom 32 bits are used to address memory. Currently, the instruction emulation code writes the truncated address to the RA register. This fixes it by keeping the full 64-bit EA in the instruction_op structure, truncating the address in emulate_step() where it is used to address memory, rather than in the address computations in analyse_instr(). Signed-off-by: Paul Mackerras <paulus@ozlabs.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Paul Mackerras
Michael Ellerman
parent
350779a29f
commit
d120cdbce6
@ -25,7 +25,7 @@ struct pt_regs;
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enum instruction_type {
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COMPUTE, /* arith/logical/CR op, etc. */
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LOAD,
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LOAD, /* load and store types need to be contiguous */
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LOAD_MULTI,
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LOAD_FP,
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LOAD_VMX,
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@ -52,6 +52,8 @@ enum instruction_type {
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#define INSTR_TYPE_MASK 0x1f
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#define OP_IS_LOAD_STORE(type) (LOAD <= (type) && (type) <= STCX)
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/* Compute flags, ORed in with type */
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#define SETREG 0x20
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#define SETCC 0x40
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@ -126,7 +126,7 @@ static nokprobe_inline unsigned long dform_ea(unsigned int instr,
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if (ra)
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ea += regs->gpr[ra];
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return truncate_if_32bit(regs->msr, ea);
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return ea;
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}
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#ifdef __powerpc64__
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@ -144,7 +144,7 @@ static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
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if (ra)
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ea += regs->gpr[ra];
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return truncate_if_32bit(regs->msr, ea);
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return ea;
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}
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/*
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@ -161,7 +161,7 @@ static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
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if (ra)
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ea += regs->gpr[ra];
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return truncate_if_32bit(regs->msr, ea);
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return ea;
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}
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#endif /* __powerpc64 */
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@ -180,7 +180,7 @@ static nokprobe_inline unsigned long xform_ea(unsigned int instr,
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if (ra)
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ea += regs->gpr[ra];
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return truncate_if_32bit(regs->msr, ea);
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return ea;
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}
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/*
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@ -1789,10 +1789,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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if (rb == 0)
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rb = 32; /* # bytes to load */
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op->type = MKOP(LOAD_MULTI, 0, rb);
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op->ea = 0;
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if (ra)
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op->ea = truncate_if_32bit(regs->msr,
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regs->gpr[ra]);
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op->ea = ra ? regs->gpr[ra] : 0;
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break;
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#ifdef CONFIG_PPC_FPU
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@ -1837,10 +1834,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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if (rb == 0)
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rb = 32; /* # bytes to store */
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op->type = MKOP(STORE_MULTI, 0, rb);
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op->ea = 0;
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if (ra)
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op->ea = truncate_if_32bit(regs->msr,
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regs->gpr[ra]);
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op->ea = ra ? regs->gpr[ra] : 0;
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break;
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case 790: /* lhbrx */
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@ -2407,10 +2401,11 @@ void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
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int emulate_step(struct pt_regs *regs, unsigned int instr)
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{
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struct instruction_op op;
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int r, err, size;
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int r, err, size, type;
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unsigned long val;
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unsigned int cr;
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int i, rd, nb;
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unsigned long ea;
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r = analyse_instr(&op, regs, instr);
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if (r < 0)
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@ -2422,27 +2417,33 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
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err = 0;
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size = GETSIZE(op.type);
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switch (op.type & INSTR_TYPE_MASK) {
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type = op.type & INSTR_TYPE_MASK;
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ea = op.ea;
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if (OP_IS_LOAD_STORE(type) || type == CACHEOP)
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ea = truncate_if_32bit(regs->msr, op.ea);
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switch (type) {
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case CACHEOP:
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if (!address_ok(regs, op.ea, 8))
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if (!address_ok(regs, ea, 8))
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return 0;
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switch (op.type & CACHEOP_MASK) {
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case DCBST:
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__cacheop_user_asmx(op.ea, err, "dcbst");
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__cacheop_user_asmx(ea, err, "dcbst");
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break;
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case DCBF:
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__cacheop_user_asmx(op.ea, err, "dcbf");
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__cacheop_user_asmx(ea, err, "dcbf");
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break;
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case DCBTST:
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if (op.reg == 0)
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prefetchw((void *) op.ea);
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prefetchw((void *) ea);
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break;
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case DCBT:
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if (op.reg == 0)
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prefetch((void *) op.ea);
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prefetch((void *) ea);
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break;
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case ICBI:
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__cacheop_user_asmx(op.ea, err, "icbi");
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__cacheop_user_asmx(ea, err, "icbi");
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break;
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}
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if (err)
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@ -2450,29 +2451,29 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
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goto instr_done;
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case LARX:
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if (op.ea & (size - 1))
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if (ea & (size - 1))
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break; /* can't handle misaligned */
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if (!address_ok(regs, op.ea, size))
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if (!address_ok(regs, ea, size))
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return 0;
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err = 0;
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switch (size) {
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#ifdef __powerpc64__
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case 1:
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__get_user_asmx(val, op.ea, err, "lbarx");
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__get_user_asmx(val, ea, err, "lbarx");
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break;
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case 2:
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__get_user_asmx(val, op.ea, err, "lharx");
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__get_user_asmx(val, ea, err, "lharx");
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break;
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#endif
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case 4:
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__get_user_asmx(val, op.ea, err, "lwarx");
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__get_user_asmx(val, ea, err, "lwarx");
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break;
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#ifdef __powerpc64__
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case 8:
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__get_user_asmx(val, op.ea, err, "ldarx");
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__get_user_asmx(val, ea, err, "ldarx");
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break;
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case 16:
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err = do_lqarx(op.ea, ®s->gpr[op.reg]);
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err = do_lqarx(ea, ®s->gpr[op.reg]);
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goto ldst_done;
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#endif
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default:
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@ -2483,29 +2484,29 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
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goto ldst_done;
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case STCX:
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if (op.ea & (size - 1))
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if (ea & (size - 1))
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break; /* can't handle misaligned */
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if (!address_ok(regs, op.ea, size))
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if (!address_ok(regs, ea, size))
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return 0;
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err = 0;
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switch (size) {
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#ifdef __powerpc64__
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case 1:
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__put_user_asmx(op.val, op.ea, err, "stbcx.", cr);
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__put_user_asmx(op.val, ea, err, "stbcx.", cr);
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break;
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case 2:
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__put_user_asmx(op.val, op.ea, err, "stbcx.", cr);
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__put_user_asmx(op.val, ea, err, "stbcx.", cr);
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break;
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#endif
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case 4:
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__put_user_asmx(op.val, op.ea, err, "stwcx.", cr);
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__put_user_asmx(op.val, ea, err, "stwcx.", cr);
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break;
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#ifdef __powerpc64__
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case 8:
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__put_user_asmx(op.val, op.ea, err, "stdcx.", cr);
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__put_user_asmx(op.val, ea, err, "stdcx.", cr);
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break;
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case 16:
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err = do_stqcx(op.ea, regs->gpr[op.reg],
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err = do_stqcx(ea, regs->gpr[op.reg],
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regs->gpr[op.reg + 1], &cr);
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break;
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#endif
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@ -2521,11 +2522,11 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
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case LOAD:
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#ifdef __powerpc64__
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if (size == 16) {
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err = emulate_lq(regs, op.ea, op.reg);
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err = emulate_lq(regs, ea, op.reg);
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goto ldst_done;
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}
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#endif
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err = read_mem(®s->gpr[op.reg], op.ea, size, regs);
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err = read_mem(®s->gpr[op.reg], ea, size, regs);
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if (!err) {
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if (op.type & SIGNEXT)
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do_signext(®s->gpr[op.reg], size);
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@ -2539,16 +2540,16 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
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if (!(regs->msr & MSR_FP))
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return 0;
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if (size == 4)
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err = do_fp_load(op.reg, do_lfs, op.ea, size, regs);
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err = do_fp_load(op.reg, do_lfs, ea, size, regs);
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else
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err = do_fp_load(op.reg, do_lfd, op.ea, size, regs);
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err = do_fp_load(op.reg, do_lfd, ea, size, regs);
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goto ldst_done;
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#endif
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#ifdef CONFIG_ALTIVEC
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case LOAD_VMX:
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if (!(regs->msr & MSR_VEC))
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return 0;
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err = do_vec_load(op.reg, do_lvx, op.ea, regs);
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err = do_vec_load(op.reg, do_lvx, ea, regs);
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goto ldst_done;
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#endif
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#ifdef CONFIG_VSX
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@ -2565,8 +2566,8 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
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msrbit = MSR_VEC;
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if (!(regs->msr & msrbit))
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return 0;
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if (!address_ok(regs, op.ea, size) ||
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__copy_from_user(mem, (void __user *)op.ea, size))
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if (!address_ok(regs, ea, size) ||
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__copy_from_user(mem, (void __user *)ea, size))
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return 0;
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emulate_vsx_load(&op, &buf, mem);
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@ -2582,12 +2583,12 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
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nb = size - i;
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if (nb > 4)
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nb = 4;
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err = read_mem(®s->gpr[rd], op.ea, nb, regs);
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err = read_mem(®s->gpr[rd], ea, nb, regs);
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if (err)
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return 0;
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if (nb < 4) /* left-justify last bytes */
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regs->gpr[rd] <<= 32 - 8 * nb;
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op.ea += 4;
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ea += 4;
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++rd;
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}
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goto instr_done;
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@ -2595,18 +2596,18 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
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case STORE:
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#ifdef __powerpc64__
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if (size == 16) {
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err = emulate_stq(regs, op.ea, op.reg);
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err = emulate_stq(regs, ea, op.reg);
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goto ldst_done;
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}
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#endif
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if ((op.type & UPDATE) && size == sizeof(long) &&
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op.reg == 1 && op.update_reg == 1 &&
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!(regs->msr & MSR_PR) &&
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op.ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
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err = handle_stack_update(op.ea, regs);
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ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
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err = handle_stack_update(ea, regs);
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goto ldst_done;
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}
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err = write_mem(op.val, op.ea, size, regs);
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err = write_mem(op.val, ea, size, regs);
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goto ldst_done;
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#ifdef CONFIG_PPC_FPU
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@ -2614,16 +2615,16 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
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if (!(regs->msr & MSR_FP))
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return 0;
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if (size == 4)
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err = do_fp_store(op.reg, do_stfs, op.ea, size, regs);
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err = do_fp_store(op.reg, do_stfs, ea, size, regs);
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else
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err = do_fp_store(op.reg, do_stfd, op.ea, size, regs);
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err = do_fp_store(op.reg, do_stfd, ea, size, regs);
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goto ldst_done;
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#endif
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#ifdef CONFIG_ALTIVEC
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case STORE_VMX:
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if (!(regs->msr & MSR_VEC))
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return 0;
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err = do_vec_store(op.reg, do_stvx, op.ea, regs);
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err = do_vec_store(op.reg, do_stvx, ea, regs);
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goto ldst_done;
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#endif
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#ifdef CONFIG_VSX
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@ -2640,12 +2641,12 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
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msrbit = MSR_VEC;
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if (!(regs->msr & msrbit))
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return 0;
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if (!address_ok(regs, op.ea, size))
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if (!address_ok(regs, ea, size))
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return 0;
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store_vsrn(op.reg, &buf);
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emulate_vsx_store(&op, &buf, mem);
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if (__copy_to_user((void __user *)op.ea, mem, size))
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if (__copy_to_user((void __user *)ea, mem, size))
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return 0;
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goto ldst_done;
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}
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@ -2661,10 +2662,10 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
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nb = 4;
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else
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val >>= 32 - 8 * nb;
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err = write_mem(val, op.ea, nb, regs);
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err = write_mem(val, ea, nb, regs);
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if (err)
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return 0;
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op.ea += 4;
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ea += 4;
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++rd;
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}
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goto instr_done;
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