forked from Minki/linux
OMAPDSS: remove struct dss_clock_info
Remove struct dss_clock_info, as it is not usable in a case where DSS fclk comes from a dedicated PLL. Instead, just use the fclk rate in place of dss_clock_info, as that is all that's needed. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
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6e555e2752
commit
d0f58bd3bb
@ -117,7 +117,7 @@ struct dpi_clk_calc_ctx {
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/* outputs */
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struct dsi_clock_info dsi_cinfo;
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struct dss_clock_info dss_cinfo;
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unsigned long long fck;
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struct dispc_clock_info dispc_cinfo;
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};
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@ -184,12 +184,11 @@ static bool dpi_calc_pll_cb(int regn, int regm, unsigned long fint,
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dpi_calc_hsdiv_cb, ctx);
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}
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static bool dpi_calc_dss_cb(int fckd, unsigned long fck, void *data)
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static bool dpi_calc_dss_cb(unsigned long fck, void *data)
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{
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struct dpi_clk_calc_ctx *ctx = data;
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ctx->dss_cinfo.fck = fck;
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ctx->dss_cinfo.fck_div = fckd;
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ctx->fck = fck;
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return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
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dpi_calc_dispc_cb, ctx);
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@ -286,13 +285,13 @@ static int dpi_set_dispc_clk(unsigned long pck_req, unsigned long *fck,
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if (!ok)
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return -EINVAL;
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r = dss_set_clock_div(&ctx.dss_cinfo);
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r = dss_set_fck_rate(ctx.fck);
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if (r)
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return r;
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dpi.mgr_config.clock_info = ctx.dispc_cinfo;
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*fck = ctx.dss_cinfo.fck;
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*fck = ctx.fck;
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*lck_div = ctx.dispc_cinfo.lck_div;
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*pck_div = ctx.dispc_cinfo.pck_div;
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@ -495,7 +494,7 @@ static int dpi_check_timings(struct omap_dss_device *dssdev,
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if (!ok)
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return -EINVAL;
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fck = ctx.dss_cinfo.fck;
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fck = ctx.fck;
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}
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lck_div = ctx.dispc_cinfo.lck_div;
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@ -81,7 +81,6 @@ static struct {
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unsigned long cache_req_pck;
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unsigned long cache_prate;
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struct dss_clock_info cache_dss_cinfo;
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struct dispc_clock_info cache_dispc_cinfo;
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enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI];
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@ -451,29 +450,6 @@ enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
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}
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}
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/* calculate clock rates using dividers in cinfo */
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int dss_calc_clock_rates(struct dss_clock_info *cinfo)
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{
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if (dss.dpll4_m4_ck) {
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unsigned long prate;
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if (cinfo->fck_div > dss.feat->fck_div_max ||
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cinfo->fck_div == 0)
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return -EINVAL;
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prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
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cinfo->fck = prate / cinfo->fck_div *
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dss.feat->dss_fck_multiplier;
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} else {
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if (cinfo->fck_div != 0)
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return -EINVAL;
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cinfo->fck = clk_get_rate(dss.dss_clk);
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}
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return 0;
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}
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bool dss_div_calc(unsigned long fck_min, dss_div_calc_func func, void *data)
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{
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int fckd, fckd_start, fckd_stop;
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@ -485,8 +461,7 @@ bool dss_div_calc(unsigned long fck_min, dss_div_calc_func func, void *data)
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if (dss.dpll4_m4_ck == NULL) {
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fck = clk_get_rate(dss.dss_clk);
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fckd = 1;
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return func(fckd, fck, data);
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return func(fck, data);
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}
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fck_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
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@ -503,38 +478,35 @@ bool dss_div_calc(unsigned long fck_min, dss_div_calc_func func, void *data)
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for (fckd = fckd_start; fckd >= fckd_stop; --fckd) {
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fck = prate / fckd * m;
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if (func(fckd, fck, data))
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if (func(fck, data))
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return true;
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}
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return false;
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}
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int dss_set_clock_div(struct dss_clock_info *cinfo)
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int dss_set_fck_rate(unsigned long rate)
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{
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DSSDBG("set fck to %lu\n", rate);
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if (dss.dpll4_m4_ck) {
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unsigned long prate;
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unsigned m;
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int r;
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prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
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DSSDBG("dpll4_m4 = %ld\n", prate);
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m = dss.feat->dss_fck_multiplier;
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r = clk_set_rate(dss.dpll4_m4_ck,
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DIV_ROUND_UP(prate, cinfo->fck_div));
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r = clk_set_rate(dss.dpll4_m4_ck, rate * m);
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if (r)
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return r;
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} else {
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if (cinfo->fck_div != 0)
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return -EINVAL;
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}
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dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
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WARN_ONCE(dss.dss_clk_rate != cinfo->fck,
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WARN_ONCE(dss.dss_clk_rate != rate,
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"clk rate mismatch: %lu != %lu", dss.dss_clk_rate,
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cinfo->fck);
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DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
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rate);
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return 0;
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}
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@ -555,8 +527,8 @@ unsigned long dss_get_dispc_clk_rate(void)
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static int dss_setup_default_clock(void)
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{
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unsigned long max_dss_fck, prate;
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unsigned long fck;
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unsigned fck_div;
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struct dss_clock_info dss_cinfo = { 0 };
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int r;
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if (dss.dpll4_m4_ck == NULL)
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@ -568,14 +540,9 @@ static int dss_setup_default_clock(void)
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fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier,
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max_dss_fck);
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fck = prate / fck_div * dss.feat->dss_fck_multiplier;
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dss_cinfo.fck_div = fck_div;
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r = dss_calc_clock_rates(&dss_cinfo);
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if (r)
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return r;
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r = dss_set_clock_div(&dss_cinfo);
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r = dss_set_fck_rate(fck);
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if (r)
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return r;
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@ -100,14 +100,6 @@ enum dss_writeback_channel {
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DSS_WB_LCD3_MGR = 7,
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};
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struct dss_clock_info {
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/* rates that we get with dividers below */
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unsigned long fck;
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/* dividers */
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u16 fck_div;
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};
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struct dispc_clock_info {
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/* rates that we get with dividers below */
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unsigned long lck;
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@ -251,10 +243,9 @@ void dss_set_venc_output(enum omap_dss_venc_type type);
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void dss_set_dac_pwrdn_bgz(bool enable);
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unsigned long dss_get_dpll4_rate(void);
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int dss_calc_clock_rates(struct dss_clock_info *cinfo);
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int dss_set_clock_div(struct dss_clock_info *cinfo);
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int dss_set_fck_rate(unsigned long rate);
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typedef bool (*dss_div_calc_func)(int fckd, unsigned long fck, void *data);
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typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
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bool dss_div_calc(unsigned long fck_min, dss_div_calc_func func, void *data);
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/* SDI */
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@ -46,7 +46,7 @@ static struct {
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struct sdi_clk_calc_ctx {
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unsigned long pck_min, pck_max;
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struct dss_clock_info dss_cinfo;
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unsigned long long fck;
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struct dispc_clock_info dispc_cinfo;
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};
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@ -63,19 +63,18 @@ static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
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return true;
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}
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static bool dpi_calc_dss_cb(int fckd, unsigned long fck, void *data)
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static bool dpi_calc_dss_cb(unsigned long fck, void *data)
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{
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struct sdi_clk_calc_ctx *ctx = data;
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ctx->dss_cinfo.fck = fck;
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ctx->dss_cinfo.fck_div = fckd;
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ctx->fck = fck;
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return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
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dpi_calc_dispc_cb, ctx);
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}
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static int sdi_calc_clock_div(unsigned long pclk,
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struct dss_clock_info *dss_cinfo,
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unsigned long *fck,
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struct dispc_clock_info *dispc_cinfo)
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{
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int i;
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@ -100,7 +99,7 @@ static int sdi_calc_clock_div(unsigned long pclk,
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ok = dss_div_calc(ctx.pck_min, dpi_calc_dss_cb, &ctx);
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if (ok) {
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*dss_cinfo = ctx.dss_cinfo;
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*fck = ctx.fck;
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*dispc_cinfo = ctx.dispc_cinfo;
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return 0;
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}
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@ -128,7 +127,7 @@ static int sdi_display_enable(struct omap_dss_device *dssdev)
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{
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struct omap_dss_device *out = &sdi.output;
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struct omap_video_timings *t = &sdi.timings;
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struct dss_clock_info dss_cinfo;
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unsigned long fck;
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struct dispc_clock_info dispc_cinfo;
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unsigned long pck;
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int r;
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@ -150,13 +149,13 @@ static int sdi_display_enable(struct omap_dss_device *dssdev)
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t->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
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t->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
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r = sdi_calc_clock_div(t->pixel_clock * 1000, &dss_cinfo, &dispc_cinfo);
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r = sdi_calc_clock_div(t->pixel_clock * 1000, &fck, &dispc_cinfo);
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if (r)
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goto err_calc_clock_div;
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sdi.mgr_config.clock_info = dispc_cinfo;
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pck = dss_cinfo.fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div / 1000;
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pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div / 1000;
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if (pck != t->pixel_clock) {
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DSSWARN("Could not find exact pixel clock. Requested %d kHz, "
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@ -169,7 +168,7 @@ static int sdi_display_enable(struct omap_dss_device *dssdev)
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dss_mgr_set_timings(out->manager, t);
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r = dss_set_clock_div(&dss_cinfo);
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r = dss_set_fck_rate(fck);
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if (r)
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goto err_set_dss_clock_div;
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