forked from Minki/linux
i.MXC family: Adding timer support
This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Juergen Beisert
Robert Schwebel
parent
90292ea60f
commit
d0f349fbce
@ -367,6 +367,8 @@ config ARCH_NS9XXX
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config ARCH_MXC
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bool "Freescale MXC/iMX-based"
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select GENERIC_TIME
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select GENERIC_CLOCKEVENTS
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select ARCH_MTD_XIP
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select GENERIC_GPIO
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select HAVE_GPIO_LIB
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@ -4,5 +4,5 @@
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# Object file lists.
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obj-y := mm.o time.o clock.o devices.o iomux.o
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obj-y := mm.o clock.o devices.o iomux.o
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obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o
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@ -26,6 +26,7 @@
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#include <asm/hardware.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <asm/memory.h>
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#include <asm/mach/map.h>
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#include <asm/arch/common.h>
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@ -127,6 +128,16 @@ static void __init mxc_board_init(void)
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mxc_init_extuart();
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}
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static void __init mx31ads_timer_init(void)
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{
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mxc_clocks_init(26000000);
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mxc_timer_init("ipg_clk.0");
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}
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struct sys_timer mx31ads_timer = {
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.init = mx31ads_timer_init,
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};
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/*
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* The following uses standard kernel macros defined in arch.h in order to
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* initialize __mach_desc_MX31ADS data structure.
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@ -139,5 +150,5 @@ MACHINE_START(MX31ADS, "Freescale MX31ADS")
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.map_io = mx31ads_map_io,
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.init_irq = mxc_init_irq,
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.init_machine = mxc_board_init,
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.timer = &mxc_timer,
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.timer = &mx31ads_timer,
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MACHINE_END
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@ -1,148 +0,0 @@
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/*
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* System Timer Interrupt reconfigured to run in free-run mode.
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* Author: Vitaly Wool
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* Copyright 2004 MontaVista Software Inc.
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*!
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* @file time.c
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* @brief This file contains OS tick and wdog timer implementations.
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*
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* This file contains OS tick and wdog timer implementations.
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*
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* @ingroup Timers
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/hardware.h>
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#include <asm/mach/time.h>
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#include <asm/io.h>
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#include <asm/arch/common.h>
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/*!
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* This is the timer interrupt service routine to do required tasks.
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* It also services the WDOG timer at the frequency of twice per WDOG
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* timeout value. For example, if the WDOG's timeout value is 4 (2
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* seconds since the WDOG runs at 0.5Hz), it will be serviced once
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* every 2/2=1 second.
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*
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* @param irq GPT interrupt source number (not used)
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* @param dev_id this parameter is not used
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* @return always returns \b IRQ_HANDLED as defined in
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* include/linux/interrupt.h.
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*/
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static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
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{
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unsigned int next_match;
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if (__raw_readl(MXC_GPT_GPTSR) & GPTSR_OF1) {
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do {
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timer_tick();
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next_match = __raw_readl(MXC_GPT_GPTOCR1) + LATCH;
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__raw_writel(GPTSR_OF1, MXC_GPT_GPTSR);
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__raw_writel(next_match, MXC_GPT_GPTOCR1);
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} while ((signed long)(next_match -
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__raw_readl(MXC_GPT_GPTCNT)) <= 0);
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}
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return IRQ_HANDLED;
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}
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/*!
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* This function is used to obtain the number of microseconds since the last
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* timer interrupt. Note that interrupts is disabled by do_gettimeofday().
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*
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* @return the number of microseconds since the last timer interrupt.
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*/
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static unsigned long mxc_gettimeoffset(void)
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{
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unsigned long ticks_to_match, elapsed, usec, tick_usec, i;
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/* Get ticks before next timer match */
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ticks_to_match =
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__raw_readl(MXC_GPT_GPTOCR1) - __raw_readl(MXC_GPT_GPTCNT);
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/* We need elapsed ticks since last match */
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elapsed = LATCH - ticks_to_match;
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/* Now convert them to usec */
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/* Insure no overflow when calculating the usec below */
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for (i = 1, tick_usec = tick_nsec / 1000;; i *= 2) {
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tick_usec /= i;
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if ((0xFFFFFFFF / tick_usec) > elapsed)
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break;
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}
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usec = (unsigned long)(elapsed * tick_usec) / (LATCH / i);
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return usec;
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}
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/*!
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* The OS tick timer interrupt structure.
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*/
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static struct irqaction timer_irq = {
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.name = "MXC Timer Tick",
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.flags = IRQF_DISABLED | IRQF_TIMER,
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.handler = mxc_timer_interrupt
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};
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/*!
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* This function is used to initialize the GPT to produce an interrupt
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* based on HZ. It is called by start_kernel() during system startup.
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*/
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void __init mxc_init_time(void)
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{
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u32 reg, v;
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reg = __raw_readl(MXC_GPT_GPTCR);
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reg &= ~GPTCR_ENABLE;
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__raw_writel(reg, MXC_GPT_GPTCR);
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reg |= GPTCR_SWR;
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__raw_writel(reg, MXC_GPT_GPTCR);
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while ((__raw_readl(MXC_GPT_GPTCR) & GPTCR_SWR) != 0)
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cpu_relax();
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reg = GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ;
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__raw_writel(reg, MXC_GPT_GPTCR);
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/* TODO: get timer rate from clk driver */
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v = 66500000;
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__raw_writel((v / CLOCK_TICK_RATE) - 1, MXC_GPT_GPTPR);
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if ((v % CLOCK_TICK_RATE) != 0) {
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pr_info("\nWARNING: Can't generate CLOCK_TICK_RATE at %d Hz\n",
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CLOCK_TICK_RATE);
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}
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pr_info("Actual CLOCK_TICK_RATE is %d Hz\n",
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v / ((__raw_readl(MXC_GPT_GPTPR) & 0xFFF) + 1));
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reg = __raw_readl(MXC_GPT_GPTCNT);
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reg += LATCH;
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__raw_writel(reg, MXC_GPT_GPTOCR1);
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setup_irq(MXC_INT_GPT, &timer_irq);
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reg = __raw_readl(MXC_GPT_GPTCR);
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reg =
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GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ | GPTCR_STOPEN | GPTCR_DOZEN |
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GPTCR_WAITEN | GPTCR_ENMOD | GPTCR_ENABLE;
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__raw_writel(reg, MXC_GPT_GPTCR);
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__raw_writel(GPTIR_OF1IE, MXC_GPT_GPTIR);
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}
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struct sys_timer mxc_timer = {
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.init = mxc_init_time,
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.offset = mxc_gettimeoffset,
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};
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@ -3,4 +3,4 @@
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#
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# Common support
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obj-y := irq.o clock.o gpio.o
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obj-y := irq.o clock.o gpio.o time.o
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228
arch/arm/plat-mxc/time.c
Normal file
228
arch/arm/plat-mxc/time.c
Normal file
@ -0,0 +1,228 @@
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/*
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* linux/arch/arm/plat-mxc/time.c
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*
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* Copyright (C) 2000-2001 Deep Blue Solutions
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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* Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
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* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/clockchips.h>
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#include <linux/clk.h>
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#include <asm/hardware.h>
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#include <asm/mach/time.h>
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#include <asm/arch/common.h>
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#include <asm/arch/mxc_timer.h>
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static struct clock_event_device clockevent_mxc;
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static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
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/* clock source for the timer */
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static struct clk *timer_clk;
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/* clock source */
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static cycle_t mxc_get_cycles(void)
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{
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return __raw_readl(TIMER_BASE + MXC_TCN);
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}
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static struct clocksource clocksource_mxc = {
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.name = "mxc_timer1",
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.rating = 200,
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.read = mxc_get_cycles,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 20,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int __init mxc_clocksource_init(void)
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{
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unsigned int clock;
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clock = clk_get_rate(timer_clk);
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clocksource_mxc.mult = clocksource_hz2mult(clock,
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clocksource_mxc.shift);
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clocksource_register(&clocksource_mxc);
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return 0;
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}
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/* clock event */
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static int mxc_set_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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unsigned long tcmp;
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tcmp = __raw_readl(TIMER_BASE + MXC_TCN) + evt;
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__raw_writel(tcmp, TIMER_BASE + MXC_TCMP);
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return (int)(tcmp - __raw_readl(TIMER_BASE + MXC_TCN)) < 0 ?
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-ETIME : 0;
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}
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#ifdef DEBUG
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static const char *clock_event_mode_label[] = {
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[CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
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[CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
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[CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
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[CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED"
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};
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#endif /* DEBUG */
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static void mxc_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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unsigned long flags;
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/*
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* The timer interrupt generation is disabled at least
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* for enough time to call mxc_set_next_event()
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*/
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local_irq_save(flags);
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/* Disable interrupt in GPT module */
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gpt_irq_disable();
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if (mode != clockevent_mode) {
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/* Set event time into far-far future */
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__raw_writel(__raw_readl(TIMER_BASE + MXC_TCN) - 3,
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TIMER_BASE + MXC_TCMP);
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/* Clear pending interrupt */
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gpt_irq_acknowledge();
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}
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#ifdef DEBUG
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printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
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clock_event_mode_label[clockevent_mode],
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clock_event_mode_label[mode]);
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#endif /* DEBUG */
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/* Remember timer mode */
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clockevent_mode = mode;
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local_irq_restore(flags);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
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"supported for i.MX\n");
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/*
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* Do not put overhead of interrupt enable/disable into
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* mxc_set_next_event(), the core has about 4 minutes
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* to call mxc_set_next_event() or shutdown clock after
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* mode switching
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*/
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local_irq_save(flags);
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gpt_irq_enable();
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local_irq_restore(flags);
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_RESUME:
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/* Left event sources disabled, no more interrupts appear */
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break;
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}
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}
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &clockevent_mxc;
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uint32_t tstat;
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tstat = __raw_readl(TIMER_BASE + MXC_TSTAT);
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gpt_irq_acknowledge();
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction mxc_timer_irq = {
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.name = "i.MX Timer Tick",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = mxc_timer_interrupt,
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};
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static struct clock_event_device clockevent_mxc = {
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.name = "mxc_timer1",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.set_mode = mxc_set_mode,
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.set_next_event = mxc_set_next_event,
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.rating = 200,
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};
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static int __init mxc_clockevent_init(void)
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{
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unsigned int clock;
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clock = clk_get_rate(timer_clk);
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clockevent_mxc.mult = div_sc(clock, NSEC_PER_SEC,
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clockevent_mxc.shift);
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clockevent_mxc.max_delta_ns =
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clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
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clockevent_mxc.min_delta_ns =
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clockevent_delta2ns(0xff, &clockevent_mxc);
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clockevent_mxc.cpumask = cpumask_of_cpu(0);
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clockevents_register_device(&clockevent_mxc);
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return 0;
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}
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void __init mxc_timer_init(const char *clk_timer)
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{
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timer_clk = clk_get(NULL, clk_timer);
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if (!timer_clk) {
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printk(KERN_ERR"Cannot determine timer clock. Giving up.\n");
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return;
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}
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clk_enable(timer_clk);
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/*
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* Initialise to a known state (all timers off, and timing reset)
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*/
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__raw_writel(0, TIMER_BASE + MXC_TCTL);
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__raw_writel(0, TIMER_BASE + MXC_TPRER); /* see datasheet note */
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__raw_writel(TCTL_FRR | /* free running */
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TCTL_VAL | /* set clocksource and arch specific bits */
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TCTL_TEN, /* start the timer */
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TIMER_BASE + MXC_TCTL);
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/* init and register the timer to the framework */
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mxc_clocksource_init();
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mxc_clockevent_init();
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/* Make irqs happen */
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setup_irq(TIMER_INTERRUPT, &mxc_timer_irq);
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}
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@ -11,11 +11,9 @@
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#ifndef __ASM_ARCH_MXC_COMMON_H__
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#define __ASM_ARCH_MXC_COMMON_H__
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struct sys_timer;
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extern void mxc_map_io(void);
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extern void mxc_init_irq(void);
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extern struct sys_timer mxc_timer;
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extern void mxc_timer_init(const char *clk_timer);
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extern int mxc_clocks_init(unsigned long fref);
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extern int mxc_register_gpios(void);
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@ -1,11 +1,20 @@
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/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* This program is free software; you can redistribute it and/or modify
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||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MXC_H__
|
||||
@ -20,97 +29,6 @@
|
||||
# define cpu_is_mx31() (0)
|
||||
#endif
|
||||
|
||||
/*
|
||||
*****************************************
|
||||
* GPT Register definitions *
|
||||
*****************************************
|
||||
*/
|
||||
#define MXC_GPT_GPTCR IO_ADDRESS(GPT1_BASE_ADDR + 0x00)
|
||||
#define MXC_GPT_GPTPR IO_ADDRESS(GPT1_BASE_ADDR + 0x04)
|
||||
#define MXC_GPT_GPTSR IO_ADDRESS(GPT1_BASE_ADDR + 0x08)
|
||||
#define MXC_GPT_GPTIR IO_ADDRESS(GPT1_BASE_ADDR + 0x0C)
|
||||
#define MXC_GPT_GPTOCR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x10)
|
||||
#define MXC_GPT_GPTOCR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x14)
|
||||
#define MXC_GPT_GPTOCR3 IO_ADDRESS(GPT1_BASE_ADDR + 0x18)
|
||||
#define MXC_GPT_GPTICR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x1C)
|
||||
#define MXC_GPT_GPTICR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
|
||||
#define MXC_GPT_GPTCNT IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
|
||||
|
||||
/* GPT Control register bit definitions */
|
||||
#define GPTCR_FO3 (1 << 31)
|
||||
#define GPTCR_FO2 (1 << 30)
|
||||
#define GPTCR_FO1 (1 << 29)
|
||||
|
||||
#define GPTCR_OM3_SHIFT 26
|
||||
#define GPTCR_OM3_MASK (7 << GPTCR_OM3_SHIFT)
|
||||
#define GPTCR_OM3_DISCONNECTED (0 << GPTCR_OM3_SHIFT)
|
||||
#define GPTCR_OM3_TOGGLE (1 << GPTCR_OM3_SHIFT)
|
||||
#define GPTCR_OM3_CLEAR (2 << GPTCR_OM3_SHIFT)
|
||||
#define GPTCR_OM3_SET (3 << GPTCR_OM3_SHIFT)
|
||||
#define GPTCR_OM3_GENERATE_LOW (7 << GPTCR_OM3_SHIFT)
|
||||
|
||||
#define GPTCR_OM2_SHIFT 23
|
||||
#define GPTCR_OM2_MASK (7 << GPTCR_OM2_SHIFT)
|
||||
#define GPTCR_OM2_DISCONNECTED (0 << GPTCR_OM2_SHIFT)
|
||||
#define GPTCR_OM2_TOGGLE (1 << GPTCR_OM2_SHIFT)
|
||||
#define GPTCR_OM2_CLEAR (2 << GPTCR_OM2_SHIFT)
|
||||
#define GPTCR_OM2_SET (3 << GPTCR_OM2_SHIFT)
|
||||
#define GPTCR_OM2_GENERATE_LOW (7 << GPTCR_OM2_SHIFT)
|
||||
|
||||
#define GPTCR_OM1_SHIFT 20
|
||||
#define GPTCR_OM1_MASK (7 << GPTCR_OM1_SHIFT)
|
||||
#define GPTCR_OM1_DISCONNECTED (0 << GPTCR_OM1_SHIFT)
|
||||
#define GPTCR_OM1_TOGGLE (1 << GPTCR_OM1_SHIFT)
|
||||
#define GPTCR_OM1_CLEAR (2 << GPTCR_OM1_SHIFT)
|
||||
#define GPTCR_OM1_SET (3 << GPTCR_OM1_SHIFT)
|
||||
#define GPTCR_OM1_GENERATE_LOW (7 << GPTCR_OM1_SHIFT)
|
||||
|
||||
#define GPTCR_IM2_SHIFT 18
|
||||
#define GPTCR_IM2_MASK (3 << GPTCR_IM2_SHIFT)
|
||||
#define GPTCR_IM2_CAPTURE_DISABLE (0 << GPTCR_IM2_SHIFT)
|
||||
#define GPTCR_IM2_CAPTURE_RISING (1 << GPTCR_IM2_SHIFT)
|
||||
#define GPTCR_IM2_CAPTURE_FALLING (2 << GPTCR_IM2_SHIFT)
|
||||
#define GPTCR_IM2_CAPTURE_BOTH (3 << GPTCR_IM2_SHIFT)
|
||||
|
||||
#define GPTCR_IM1_SHIFT 16
|
||||
#define GPTCR_IM1_MASK (3 << GPTCR_IM1_SHIFT)
|
||||
#define GPTCR_IM1_CAPTURE_DISABLE (0 << GPTCR_IM1_SHIFT)
|
||||
#define GPTCR_IM1_CAPTURE_RISING (1 << GPTCR_IM1_SHIFT)
|
||||
#define GPTCR_IM1_CAPTURE_FALLING (2 << GPTCR_IM1_SHIFT)
|
||||
#define GPTCR_IM1_CAPTURE_BOTH (3 << GPTCR_IM1_SHIFT)
|
||||
|
||||
#define GPTCR_SWR (1 << 15)
|
||||
#define GPTCR_FRR (1 << 9)
|
||||
|
||||
#define GPTCR_CLKSRC_SHIFT 6
|
||||
#define GPTCR_CLKSRC_MASK (7 << GPTCR_CLKSRC_SHIFT)
|
||||
#define GPTCR_CLKSRC_NOCLOCK (0 << GPTCR_CLKSRC_SHIFT)
|
||||
#define GPTCR_CLKSRC_HIGHFREQ (2 << GPTCR_CLKSRC_SHIFT)
|
||||
#define GPTCR_CLKSRC_CLKIN (3 << GPTCR_CLKSRC_SHIFT)
|
||||
#define GPTCR_CLKSRC_CLK32K (7 << GPTCR_CLKSRC_SHIFT)
|
||||
|
||||
#define GPTCR_STOPEN (1 << 5)
|
||||
#define GPTCR_DOZEN (1 << 4)
|
||||
#define GPTCR_WAITEN (1 << 3)
|
||||
#define GPTCR_DBGEN (1 << 2)
|
||||
|
||||
#define GPTCR_ENMOD (1 << 1)
|
||||
#define GPTCR_ENABLE (1 << 0)
|
||||
|
||||
#define GPTSR_OF1 (1 << 0)
|
||||
#define GPTSR_OF2 (1 << 1)
|
||||
#define GPTSR_OF3 (1 << 2)
|
||||
#define GPTSR_IF1 (1 << 3)
|
||||
#define GPTSR_IF2 (1 << 4)
|
||||
#define GPTSR_ROV (1 << 5)
|
||||
|
||||
#define GPTIR_OF1IE GPTSR_OF1
|
||||
#define GPTIR_OF2IE GPTSR_OF2
|
||||
#define GPTIR_OF3IE GPTSR_OF3
|
||||
#define GPTIR_IF1IE GPTSR_IF1
|
||||
#define GPTIR_IF2IE GPTSR_IF2
|
||||
#define GPTIR_ROVIE GPTSR_ROV
|
||||
|
||||
/*
|
||||
*****************************************
|
||||
* AVIC Registers *
|
||||
|
||||
158
include/asm-arm/arch-mxc/mxc_timer.h
Normal file
158
include/asm-arm/arch-mxc/mxc_timer.h
Normal file
@ -0,0 +1,158 @@
|
||||
/*
|
||||
* mxc_timer.h
|
||||
*
|
||||
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
|
||||
*
|
||||
* Platform independent (i.MX1, i.MX2, i.MX3) definition for timer handling.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_MXC_TIMER_H
|
||||
#define __PLAT_MXC_TIMER_H
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#ifdef CONFIG_ARCH_IMX
|
||||
#define TIMER_BASE IO_ADDRESS(TIM1_BASE_ADDR)
|
||||
#define TIMER_INTERRUPT TIM1_INT
|
||||
|
||||
#define TCTL_VAL TCTL_CLK_PCLK1
|
||||
#define TCTL_IRQEN (1<<4)
|
||||
#define TCTL_FRR (1<<8)
|
||||
#define TCTL_CLK_PCLK1 (1<<1)
|
||||
#define TCTL_CLK_PCLK1_4 (2<<1)
|
||||
#define TCTL_CLK_TIN (3<<1)
|
||||
#define TCTL_CLK_32 (4<<1)
|
||||
|
||||
#define MXC_TCTL 0x00
|
||||
#define MXC_TPRER 0x04
|
||||
#define MXC_TCMP 0x08
|
||||
#define MXC_TCR 0x0c
|
||||
#define MXC_TCN 0x10
|
||||
#define MXC_TSTAT 0x14
|
||||
#define TSTAT_CAPT (1<<1)
|
||||
#define TSTAT_COMP (1<<0)
|
||||
|
||||
static inline void gpt_irq_disable(void)
|
||||
{
|
||||
unsigned int tmp;
|
||||
|
||||
tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
|
||||
__raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
|
||||
}
|
||||
|
||||
static inline void gpt_irq_enable(void)
|
||||
{
|
||||
__raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
|
||||
TIMER_BASE + MXC_TCTL);
|
||||
}
|
||||
|
||||
static void gpt_irq_acknowledge(void)
|
||||
{
|
||||
__raw_writel(0, TIMER_BASE + MXC_TSTAT);
|
||||
}
|
||||
#endif /* CONFIG_ARCH_IMX */
|
||||
|
||||
#ifdef CONFIG_ARCH_MX2
|
||||
#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR)
|
||||
#define TIMER_INTERRUPT MXC_INT_GPT1
|
||||
|
||||
#define MXC_TCTL 0x00
|
||||
#define TCTL_VAL TCTL_CLK_PCLK1
|
||||
#define TCTL_CLK_PCLK1 (1<<1)
|
||||
#define TCTL_CLK_PCLK1_4 (2<<1)
|
||||
#define TCTL_IRQEN (1<<4)
|
||||
#define TCTL_FRR (1<<8)
|
||||
#define MXC_TPRER 0x04
|
||||
#define MXC_TCMP 0x08
|
||||
#define MXC_TCR 0x0c
|
||||
#define MXC_TCN 0x10
|
||||
#define MXC_TSTAT 0x14
|
||||
#define TSTAT_CAPT (1<<1)
|
||||
#define TSTAT_COMP (1<<0)
|
||||
|
||||
static inline void gpt_irq_disable(void)
|
||||
{
|
||||
unsigned int tmp;
|
||||
|
||||
tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
|
||||
__raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
|
||||
}
|
||||
|
||||
static inline void gpt_irq_enable(void)
|
||||
{
|
||||
__raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
|
||||
TIMER_BASE + MXC_TCTL);
|
||||
}
|
||||
|
||||
static void gpt_irq_acknowledge(void)
|
||||
{
|
||||
__raw_writel(TSTAT_CAPT | TSTAT_COMP, TIMER_BASE + MXC_TSTAT);
|
||||
}
|
||||
#endif /* CONFIG_ARCH_MX2 */
|
||||
|
||||
#ifdef CONFIG_ARCH_MX3
|
||||
#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR)
|
||||
#define TIMER_INTERRUPT MXC_INT_GPT
|
||||
|
||||
#define MXC_TCTL 0x00
|
||||
#define TCTL_VAL (TCTL_CLK_IPG | TCTL_WAITEN)
|
||||
#define TCTL_CLK_IPG (1<<6)
|
||||
#define TCTL_FRR (1<<9)
|
||||
#define TCTL_WAITEN (1<<3)
|
||||
|
||||
#define MXC_TPRER 0x04
|
||||
#define MXC_TSTAT 0x08
|
||||
#define TSTAT_OF1 (1<<0)
|
||||
#define TSTAT_OF2 (1<<1)
|
||||
#define TSTAT_OF3 (1<<2)
|
||||
#define TSTAT_IF1 (1<<3)
|
||||
#define TSTAT_IF2 (1<<4)
|
||||
#define TSTAT_ROV (1<<5)
|
||||
#define MXC_IR 0x0c
|
||||
#define MXC_TCMP 0x10
|
||||
#define MXC_TCMP2 0x14
|
||||
#define MXC_TCMP3 0x18
|
||||
#define MXC_TCR 0x1c
|
||||
#define MXC_TCN 0x24
|
||||
|
||||
static inline void gpt_irq_disable(void)
|
||||
{
|
||||
__raw_writel(0, TIMER_BASE + MXC_IR);
|
||||
}
|
||||
|
||||
static inline void gpt_irq_enable(void)
|
||||
{
|
||||
__raw_writel(1<<0, TIMER_BASE + MXC_IR);
|
||||
}
|
||||
|
||||
static inline void gpt_irq_acknowledge(void)
|
||||
{
|
||||
__raw_writel(TSTAT_OF1, TIMER_BASE + MXC_TSTAT);
|
||||
}
|
||||
#endif /* CONFIG_ARCH_MX3 */
|
||||
|
||||
#define TCTL_SWR (1<<15)
|
||||
#define TCTL_CC (1<<10)
|
||||
#define TCTL_OM (1<<9)
|
||||
#define TCTL_CAP_RIS (1<<6)
|
||||
#define TCTL_CAP_FAL (2<<6)
|
||||
#define TCTL_CAP_RIS_FAL (3<<6)
|
||||
#define TCTL_CAP_ENA (1<<5)
|
||||
#define TCTL_TEN (1<<0)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user