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coresight: no-op refactor to make INSTP0 check more idiomatic

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The spec says this:

  P0 tracing support field. The permitted values are:
      0b00  Tracing of load and store instructions as P0 elements is not
            supported.
      0b11  Tracing of load and store instructions as P0 elements is
            supported, so TRCCONFIGR.INSTP0 is supported.

            All other values are reserved.

The value we are looking for is 0b11 so simplify this. The double read
and && was a bit obfuscated.

Suggested-by: Suzuki Poulose <suzuki.poulose@arm.com>
Signed-off-by: James Clark <james.clark@arm.com>
Link: https://lore.kernel.org/r/20220203115336.119735-2-james.clark@arm.com
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
This commit is contained in:
James Clark 2022-02-03 11:53:35 +00:00 committed by Suzuki K Poulose
parent 27caf7e473
commit d05bbad013
1 changed files with 1 additions and 1 deletions
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2
drivers/hwtracing/coresight/coresight-etm4x-core.c
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@ -1091,7 +1091,7 @@ static void etm4_init_arch_data(void *info)
etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
/* INSTP0, bits[2:1] P0 tracing support field */
if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
if (BMVAL(etmidr0, 1, 2) == 0b11)
drvdata->instrp0 = true;
else
drvdata->instrp0 = false;