forked from Minki/linux
dt-bindings: clock: add QCOM SM8150 and SM8250 display clock bindings
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM8150 and SM8250 SoCs. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> (SM8250) Link: https://lore.kernel.org/r/20200927190653.13876-2-jonathan@marek.ca Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Jonathan Marek
Stephen Boyd
parent
0e94711a1f
commit
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
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maintainers:
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- Jonathan Marek <jonathan@marek.ca>
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description: |
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Qualcomm display clock control module which supports the clocks, resets and
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power domains on SM8150 and SM8250.
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See also:
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dt-bindings/clock/qcom,dispcc-sm8150.h
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dt-bindings/clock/qcom,dispcc-sm8250.h
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properties:
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compatible:
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enum:
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- qcom,sm8150-dispcc
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- qcom,sm8250-dispcc
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clocks:
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items:
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- description: Board XO source
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY0
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- description: Byte clock from DSI PHY1
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- description: Pixel clock from DSI PHY1
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- description: Link clock from DP PHY
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- description: VCO DIV clock from DP PHY
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clock-names:
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items:
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- const: bi_tcxo
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- const: dsi0_phy_pll_out_byteclk
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- const: dsi0_phy_pll_out_dsiclk
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- const: dsi1_phy_pll_out_byteclk
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- const: dsi1_phy_pll_out_dsiclk
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- const: dp_phy_pll_link_clk
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- const: dp_phy_pll_vco_div_clk
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@af00000 {
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compatible = "qcom,sm8250-dispcc";
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reg = <0x0af00000 0x10000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&dsi0_phy 0>,
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<&dsi0_phy 1>,
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<&dsi1_phy 0>,
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<&dsi1_phy 1>,
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<&dp_phy 0>,
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<&dp_phy 1>;
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clock-names = "bi_tcxo",
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"dsi0_phy_pll_out_byteclk",
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"dsi0_phy_pll_out_dsiclk",
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"dsi1_phy_pll_out_byteclk",
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"dsi1_phy_pll_out_dsiclk",
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"dp_phy_pll_link_clk",
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"dp_phy_pll_vco_div_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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1
include/dt-bindings/clock/qcom,dispcc-sm8150.h
Symbolic link
1
include/dt-bindings/clock/qcom,dispcc-sm8150.h
Symbolic link
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qcom,dispcc-sm8250.h
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66
include/dt-bindings/clock/qcom,dispcc-sm8250.h
Normal file
66
include/dt-bindings/clock/qcom,dispcc-sm8250.h
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
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#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
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/* DISP_CC clock registers */
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#define DISP_CC_MDSS_AHB_CLK 0
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#define DISP_CC_MDSS_AHB_CLK_SRC 1
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#define DISP_CC_MDSS_BYTE0_CLK 2
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 3
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 4
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 5
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#define DISP_CC_MDSS_BYTE1_CLK 6
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#define DISP_CC_MDSS_BYTE1_CLK_SRC 7
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#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 8
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#define DISP_CC_MDSS_BYTE1_INTF_CLK 9
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#define DISP_CC_MDSS_DP_AUX1_CLK 10
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#define DISP_CC_MDSS_DP_AUX1_CLK_SRC 11
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#define DISP_CC_MDSS_DP_AUX_CLK 12
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#define DISP_CC_MDSS_DP_AUX_CLK_SRC 13
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#define DISP_CC_MDSS_DP_LINK1_CLK 14
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#define DISP_CC_MDSS_DP_LINK1_CLK_SRC 15
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#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC 16
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#define DISP_CC_MDSS_DP_LINK1_INTF_CLK 17
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#define DISP_CC_MDSS_DP_LINK_CLK 18
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#define DISP_CC_MDSS_DP_LINK_CLK_SRC 19
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#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 20
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#define DISP_CC_MDSS_DP_LINK_INTF_CLK 21
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#define DISP_CC_MDSS_DP_PIXEL1_CLK 22
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#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 23
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#define DISP_CC_MDSS_DP_PIXEL2_CLK 24
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#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC 25
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#define DISP_CC_MDSS_DP_PIXEL_CLK 26
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#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 27
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#define DISP_CC_MDSS_ESC0_CLK 28
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#define DISP_CC_MDSS_ESC0_CLK_SRC 29
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#define DISP_CC_MDSS_ESC1_CLK 30
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#define DISP_CC_MDSS_ESC1_CLK_SRC 31
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#define DISP_CC_MDSS_MDP_CLK 32
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#define DISP_CC_MDSS_MDP_CLK_SRC 33
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#define DISP_CC_MDSS_MDP_LUT_CLK 34
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 35
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#define DISP_CC_MDSS_PCLK0_CLK 36
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 37
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#define DISP_CC_MDSS_PCLK1_CLK 38
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#define DISP_CC_MDSS_PCLK1_CLK_SRC 39
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#define DISP_CC_MDSS_ROT_CLK 40
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#define DISP_CC_MDSS_ROT_CLK_SRC 41
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#define DISP_CC_MDSS_RSCC_AHB_CLK 42
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#define DISP_CC_MDSS_RSCC_VSYNC_CLK 43
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#define DISP_CC_MDSS_VSYNC_CLK 44
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 45
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#define DISP_CC_PLL0 46
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#define DISP_CC_PLL1 47
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/* DISP_CC Reset */
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#define DISP_CC_MDSS_CORE_BCR 0
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#define DISP_CC_MDSS_RSCC_BCR 1
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/* DISP_CC GDSCR */
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#define MDSS_GDSC 0
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#endif
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