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drm/nouveau/gr/gf100-: port zcull tile mapping calculations from NVGPU

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2018-05-08 20:39:47 +10:00
parent 5f6474a4e6
commit d00ffc0c40
2 changed files with 32 additions and 32 deletions
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32
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
View File

@ -2042,25 +2042,25 @@ gf100_gr_init_zcull(struct gf100_gr *gr)
{ {
struct nvkm_device *device = gr->base.engine.subdev.device; struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
u32 data[TPC_MAX / 8] = {}; const u8 tile_nr = ALIGN(gr->tpc_total, 32);
u8 tpcnr[GPC_MAX]; u8 bank[GPC_MAX] = {}, gpc, i, j;
int gpc, tpc; u32 data;
int i;
memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); for (i = 0; i < tile_nr; i += 8) {
for (i = 0, gpc = -1; i < gr->tpc_total; i++) { for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) {
do { data |= bank[gr->tile[i + j]] << (j * 4);
gpc = (gpc + 1) % gr->gpc_nr; bank[gr->tile[i + j]]++;
} while (!tpcnr[gpc]); }
tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data);
data[i / 8] |= tpc << ((i % 8) * 4);
} }
nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
nvkm_wr32(device, GPC_BCAST(0x0988), data[2]); gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
nvkm_wr32(device, GPC_BCAST(0x098c), data[3]); nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
gr->tpc_total);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
}
nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918); nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918);
} }

32
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c
View File

@ -125,25 +125,25 @@ gf117_gr_init_zcull(struct gf100_gr *gr)
{ {
struct nvkm_device *device = gr->base.engine.subdev.device; struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
u32 data[TPC_MAX / 8] = {}; const u8 tile_nr = ALIGN(gr->tpc_total, 32);
u8 tpcnr[GPC_MAX]; u8 bank[GPC_MAX] = {}, gpc, i, j;
int gpc, tpc; u32 data;
int i;
memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); for (i = 0; i < tile_nr; i += 8) {
for (i = 0, gpc = -1; i < gr->tpc_total; i++) { for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) {
do { data |= bank[gr->tile[i + j]] << (j * 4);
gpc = (gpc + 1) % gr->gpc_nr; bank[gr->tile[i + j]]++;
} while (!tpcnr[gpc]); }
tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data);
data[i / 8] |= tpc << ((i % 8) * 4);
} }
nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
nvkm_wr32(device, GPC_BCAST(0x0988), data[2]); gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
nvkm_wr32(device, GPC_BCAST(0x098c), data[3]); nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
gr->tpc_total);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
}
nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
} }