forked from Minki/linux
drm/i915/gvt: Remove MMIO barrier in MMIO switch
After engine mmio switched, software still need write workload submission registers. So we can remove the MMIO barriar in MMIO switch. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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83164886e4
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cf27b95034
@ -275,7 +275,6 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id)
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u32 ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL];
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u32 inhibit_mask =
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_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
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i915_reg_t last_reg = _MMIO(0);
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struct engine_mmio *mmio;
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u32 v;
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@ -305,17 +304,12 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id)
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v = vgpu_vreg(vgpu, mmio->reg);
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I915_WRITE_FW(mmio->reg, v);
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last_reg = mmio->reg;
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trace_render_mmio(vgpu->id, "load",
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i915_mmio_reg_offset(mmio->reg),
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mmio->value, v);
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}
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/* Make sure the swiched MMIOs has taken effect. */
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if (likely(i915_mmio_reg_offset(last_reg)))
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I915_READ_FW(last_reg);
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handle_tlb_pending_event(vgpu, ring_id);
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}
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@ -323,7 +317,6 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id)
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static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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i915_reg_t last_reg = _MMIO(0);
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struct engine_mmio *mmio;
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u32 v;
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@ -347,16 +340,11 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id)
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continue;
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I915_WRITE_FW(mmio->reg, v);
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last_reg = mmio->reg;
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trace_render_mmio(vgpu->id, "restore",
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i915_mmio_reg_offset(mmio->reg),
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mmio->value, v);
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}
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/* Make sure the swiched MMIOs has taken effect. */
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if (likely(i915_mmio_reg_offset(last_reg)))
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I915_READ_FW(last_reg);
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}
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/**
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