forked from Minki/linux
drm/nva3/pm: tidy and add some comments here and there
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
4fd2847e9b
commit
cec2a270db
@ -28,15 +28,15 @@
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#include "nouveau_pm.h"
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static u32 read_clk(struct drm_device *, int, bool);
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static u32 read_pll(struct drm_device *, u32, int);
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static u32 read_pll(struct drm_device *, int, u32);
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static u32
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read_vco(struct drm_device *dev, int clk)
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{
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u32 sctl = nv_rd32(dev, 0x4120 + (clk * 4));
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if ((sctl & 0x00000030) != 0x00000030)
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return read_pll(dev, 0x00e820, 0x41);
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return read_pll(dev, 0x00e8a0, 0x42);
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return read_pll(dev, 0x41, 0x00e820);
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return read_pll(dev, 0x42, 0x00e8a0);
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}
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static u32
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@ -44,6 +44,7 @@ read_clk(struct drm_device *dev, int clk, bool ignore_en)
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{
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u32 sctl, sdiv, sclk;
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/* refclk for the 0xe8xx plls always 27KHz */
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if (clk >= 0x40)
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return 27000;
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@ -68,7 +69,7 @@ read_clk(struct drm_device *dev, int clk, bool ignore_en)
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}
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static u32
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read_pll(struct drm_device *dev, u32 pll, int clk)
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read_pll(struct drm_device *dev, int clk, u32 pll)
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{
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u32 ctrl = nv_rd32(dev, pll + 0);
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u32 sclk, P = 1, N = 1, M = 1;
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@ -78,6 +79,8 @@ read_pll(struct drm_device *dev, u32 pll, int clk)
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M = (coef & 0x000000ff) >> 0;
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N = (coef & 0x0000ff00) >> 8;
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P = (coef & 0x003f0000) >> 16;
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/* not post-divider on these.. */
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if ((pll & 0x00ff00) == 0x00e800)
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P = 1;
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@ -95,7 +98,7 @@ struct creg {
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};
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static int
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calc_clk(struct drm_device *dev, u32 pll, int clk, u32 khz, struct creg *reg)
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calc_clk(struct drm_device *dev, int clk, u32 pll, u32 khz, struct creg *reg)
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{
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struct pll_lims limits;
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u32 oclk, sclk, sdiv;
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@ -104,6 +107,10 @@ calc_clk(struct drm_device *dev, u32 pll, int clk, u32 khz, struct creg *reg)
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reg->pll = 0;
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reg->clk = 0;
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if (!khz) {
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NV_DEBUG(dev, "no clock for 0x%04x/0x%02x\n", pll, clk);
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return 0;
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}
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switch (khz) {
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case 27000:
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@ -118,6 +125,14 @@ calc_clk(struct drm_device *dev, u32 pll, int clk, u32 khz, struct creg *reg)
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default:
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sclk = read_vco(dev, clk);
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sdiv = min((sclk * 2) / (khz - 2999), (u32)65);
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/* if the clock has a PLL attached, and we can get a within
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* [-2, 3) MHz of a divider, we'll disable the PLL and use
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* the divider instead.
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*
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* divider can go as low as 2, limited here because NVIDIA
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* and the VBIOS on my NVA8 seem to prefer using the PLL
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* for 810MHz - is there a good reason?
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*/
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if (sdiv > 4) {
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oclk = (sclk * 2) / sdiv;
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diff = khz - oclk;
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@ -126,6 +141,12 @@ calc_clk(struct drm_device *dev, u32 pll, int clk, u32 khz, struct creg *reg)
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return oclk;
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}
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}
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if (!pll) {
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NV_ERROR(dev, "bad freq %02x: %d %d\n", clk, khz, sclk);
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return -ERANGE;
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}
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break;
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}
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@ -145,12 +166,53 @@ calc_clk(struct drm_device *dev, u32 pll, int clk, u32 khz, struct creg *reg)
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return ret;
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}
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static void
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prog_pll(struct drm_device *dev, int clk, u32 pll, struct creg *reg)
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{
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const u32 src0 = 0x004120 + (clk * 4);
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const u32 src1 = 0x004160 + (clk * 4);
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const u32 ctrl = pll + 0;
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const u32 coef = pll + 4;
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u32 cntl;
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if (!reg->clk && !reg->pll) {
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NV_DEBUG(dev, "no clock for %02x\n", clk);
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return;
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}
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cntl = nv_rd32(dev, ctrl) & 0xfffffff2;
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if (reg->pll) {
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nv_mask(dev, src0, 0x00000101, 0x00000101);
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nv_wr32(dev, coef, reg->pll);
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nv_wr32(dev, ctrl, cntl | 0x00000015);
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nv_mask(dev, src1, 0x00000100, 0x00000000);
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nv_mask(dev, src1, 0x00000001, 0x00000000);
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} else {
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nv_mask(dev, src1, 0x003f3141, 0x00000101 | reg->clk);
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nv_wr32(dev, ctrl, cntl | 0x0000001d);
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nv_mask(dev, ctrl, 0x00000001, 0x00000000);
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nv_mask(dev, src0, 0x00000100, 0x00000000);
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nv_mask(dev, src0, 0x00000001, 0x00000000);
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}
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}
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static void
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prog_clk(struct drm_device *dev, int clk, struct creg *reg)
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{
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if (!reg->clk) {
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NV_DEBUG(dev, "no clock for %02x\n", clk);
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return;
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}
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nv_mask(dev, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | reg->clk);
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}
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int
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nva3_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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{
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perflvl->core = read_pll(dev, 0x4200, 0);
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perflvl->shader = read_pll(dev, 0x4220, 1);
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perflvl->memory = read_pll(dev, 0x4000, 2);
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perflvl->core = read_pll(dev, 0x00, 0x4200);
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perflvl->shader = read_pll(dev, 0x01, 0x4220);
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perflvl->memory = read_pll(dev, 0x02, 0x4000);
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perflvl->unka0 = read_clk(dev, 0x20, false);
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perflvl->vdec = read_clk(dev, 0x21, false);
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return 0;
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@ -174,23 +236,23 @@ nva3_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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if (!info)
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return ERR_PTR(-ENOMEM);
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ret = calc_clk(dev, 0x4200, 0x10, perflvl->core, &info->nclk);
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ret = calc_clk(dev, 0x10, 0x4200, perflvl->core, &info->nclk);
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if (ret < 0)
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goto out;
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ret = calc_clk(dev, 0x4220, 0x11, perflvl->shader, &info->sclk);
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ret = calc_clk(dev, 0x11, 0x4220, perflvl->shader, &info->sclk);
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if (ret < 0)
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goto out;
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ret = calc_clk(dev, 0x4000, 0x12, perflvl->memory, &info->mclk);
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ret = calc_clk(dev, 0x12, 0x4000, perflvl->memory, &info->mclk);
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if (ret < 0)
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goto out;
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ret = calc_clk(dev, 0x0000, 0x20, perflvl->unka0, &info->unka0);
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ret = calc_clk(dev, 0x20, 0x0000, perflvl->unka0, &info->unka0);
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if (ret < 0)
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goto out;
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ret = calc_clk(dev, 0x0000, 0x21, perflvl->vdec, &info->vdec);
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ret = calc_clk(dev, 0x21, 0x0000, perflvl->vdec, &info->vdec);
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if (ret < 0)
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goto out;
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@ -202,51 +264,20 @@ out:
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return info;
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}
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static void
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prog_pll(struct drm_device *dev, u32 pll, int clk, struct creg *reg)
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{
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const u32 src0 = 0x004120 + (clk * 4);
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const u32 src1 = 0x004160 + (clk * 4);
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const u32 ctrl = pll + 0;
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const u32 coef = pll + 4;
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u32 cntl;
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cntl = nv_rd32(dev, ctrl) & 0xfffffff2;
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if (reg->pll) {
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nv_mask(dev, src0, 0x00000101, 0x00000101);
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nv_wr32(dev, coef, reg->pll);
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nv_wr32(dev, ctrl, cntl | 0x00000015);
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nv_mask(dev, src1, 0x00000100, 0x00000000);
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nv_mask(dev, src1, 0x00000001, 0x00000000);
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} else {
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nv_mask(dev, src1, 0x003f3141, 0x00000101 | reg->clk);
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nv_wr32(dev, ctrl, cntl | 0x0000001d);
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nv_mask(dev, ctrl, 0x00000001, 0x00000000);
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nv_mask(dev, src0, 0x00000100, 0x00000000);
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nv_mask(dev, src0, 0x00000001, 0x00000000);
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}
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}
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static void
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prog_clk(struct drm_device *dev, int clk, struct creg *reg)
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{
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nv_mask(dev, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | reg->clk);
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}
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void
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nva3_pm_clocks_set(struct drm_device *dev, void *pre_state)
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{
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struct nva3_pm_state *info = pre_state;
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prog_pll(dev, 0x004200, 0, &info->nclk);
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prog_pll(dev, 0x004220, 1, &info->sclk);
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prog_pll(dev, 0x00, 0x004200, &info->nclk);
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prog_pll(dev, 0x01, 0x004220, &info->sclk);
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prog_clk(dev, 0x20, &info->unka0);
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prog_clk(dev, 0x21, &info->vdec);
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nv_wr32(dev, 0x100210, 0);
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nv_wr32(dev, 0x1002dc, 1);
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nv_wr32(dev, 0x004018, 0x00001000);
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prog_pll(dev, 0x004000, 2, &info->mclk);
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prog_pll(dev, 0x02, 0x004000, &info->mclk);
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if (nv_rd32(dev, 0x4000) & 0x00000008)
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nv_wr32(dev, 0x004018, 0x1000d000);
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else
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