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drm/amdgpu/mmhub2.0: convert to IP version checking

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Use IP versions rather than asic_type to differentiate
IP version specific features.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2021-07-27 16:21:18 -04:00
parent fac1772374
commit ce2d99a84f
1 changed files with 32 additions and 41 deletions
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73
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
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@ -153,18 +153,16 @@ mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
dev_err(adev->dev, dev_err(adev->dev,
"MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
status); status);
switch (adev->asic_type) { switch (adev->ip_versions[MMHUB_HWIP]) {
case CHIP_NAVI10: case IP_VERSION(2, 0, 0):
case CHIP_NAVI12: case IP_VERSION(2, 0, 2):
case CHIP_NAVI14:
mmhub_cid = mmhub_client_ids_navi1x[cid][rw]; mmhub_cid = mmhub_client_ids_navi1x[cid][rw];
break; break;
case CHIP_SIENNA_CICHLID: case IP_VERSION(2, 1, 0):
case CHIP_NAVY_FLOUNDER: case IP_VERSION(2, 1, 1):
case CHIP_DIMGREY_CAVEFISH:
mmhub_cid = mmhub_client_ids_sienna_cichlid[cid][rw]; mmhub_cid = mmhub_client_ids_sienna_cichlid[cid][rw];
break; break;
case CHIP_BEIGE_GOBY: case IP_VERSION(2, 1, 2):
mmhub_cid = mmhub_client_ids_beige_goby[cid][rw]; mmhub_cid = mmhub_client_ids_beige_goby[cid][rw];
break; break;
default: default:
@ -571,11 +569,10 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
return; return;
switch (adev->asic_type) { switch (adev->ip_versions[MMHUB_HWIP]) {
case CHIP_SIENNA_CICHLID: case IP_VERSION(2, 1, 0):
case CHIP_NAVY_FLOUNDER: case IP_VERSION(2, 1, 1):
case CHIP_DIMGREY_CAVEFISH: case IP_VERSION(2, 1, 2):
case CHIP_BEIGE_GOBY:
def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid); def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid); def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
break; break;
@ -606,11 +603,10 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
} }
switch (adev->asic_type) { switch (adev->ip_versions[MMHUB_HWIP]) {
case CHIP_SIENNA_CICHLID: case IP_VERSION(2, 1, 0):
case CHIP_NAVY_FLOUNDER: case IP_VERSION(2, 1, 1):
case CHIP_DIMGREY_CAVEFISH: case IP_VERSION(2, 1, 2):
case CHIP_BEIGE_GOBY:
if (def != data) if (def != data)
WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data); WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
if (def1 != data1) if (def1 != data1)
@ -633,11 +629,10 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
return; return;
switch (adev->asic_type) { switch (adev->ip_versions[MMHUB_HWIP]) {
case CHIP_SIENNA_CICHLID: case IP_VERSION(2, 1, 0):
case CHIP_NAVY_FLOUNDER: case IP_VERSION(2, 1, 1):
case CHIP_DIMGREY_CAVEFISH: case IP_VERSION(2, 1, 2):
case CHIP_BEIGE_GOBY:
def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid); def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
break; break;
default: default:
@ -651,11 +646,10 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
if (def != data) { if (def != data) {
switch (adev->asic_type) { switch (adev->ip_versions[MMHUB_HWIP]) {
case CHIP_SIENNA_CICHLID: case IP_VERSION(2, 1, 0):
case CHIP_NAVY_FLOUNDER: case IP_VERSION(2, 1, 1):
case CHIP_DIMGREY_CAVEFISH: case IP_VERSION(2, 1, 2):
case CHIP_BEIGE_GOBY:
WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data); WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
break; break;
default: default:
@ -671,14 +665,12 @@ static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
if (amdgpu_sriov_vf(adev)) if (amdgpu_sriov_vf(adev))
return 0; return 0;
switch (adev->asic_type) { switch (adev->ip_versions[MMHUB_HWIP]) {
case CHIP_NAVI10: case IP_VERSION(2, 0, 0):
case CHIP_NAVI14: case IP_VERSION(2, 0, 2):
case CHIP_NAVI12: case IP_VERSION(2, 1, 0):
case CHIP_SIENNA_CICHLID: case IP_VERSION(2, 1, 1):
case CHIP_NAVY_FLOUNDER: case IP_VERSION(2, 1, 2):
case CHIP_DIMGREY_CAVEFISH:
case CHIP_BEIGE_GOBY:
mmhub_v2_0_update_medium_grain_clock_gating(adev, mmhub_v2_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE); state == AMD_CG_STATE_GATE);
mmhub_v2_0_update_medium_grain_light_sleep(adev, mmhub_v2_0_update_medium_grain_light_sleep(adev,
@ -698,11 +690,10 @@ static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
if (amdgpu_sriov_vf(adev)) if (amdgpu_sriov_vf(adev))
*flags = 0; *flags = 0;
switch (adev->asic_type) { switch (adev->ip_versions[MMHUB_HWIP]) {
case CHIP_SIENNA_CICHLID: case IP_VERSION(2, 1, 0):
case CHIP_NAVY_FLOUNDER: case IP_VERSION(2, 1, 1):
case CHIP_DIMGREY_CAVEFISH: case IP_VERSION(2, 1, 2):
case CHIP_BEIGE_GOBY:
data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid); data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid); data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
break; break;