forked from Minki/linux
MIPS: Alchemy: support multiple GPIO styles in one kernel
For GPIOLIB=y decide at runtime which gpiochips to register; in the GPIOLIB=n case, the gpio headers need to be reshuffled a bit to make multiple implementations coexist peacefully. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2679/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss
Ralf Baechle
parent
2e8fd2e5ef
commit
ce1d43b9a9
@ -12,9 +12,7 @@ obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o
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# optional gpiolib support
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ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
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ifeq ($(CONFIG_GPIOLIB),y)
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obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += gpiolib-au1000.o
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endif
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obj-$(CONFIG_GPIOLIB) += gpiolib.o
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endif
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obj-$(CONFIG_PCI) += pci.o
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@ -1,6 +1,6 @@
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/*
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* Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
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* GPIOLIB support for Au1000, Au1500, Au1100, Au1550 and Au12x0.
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* GPIOLIB support for Alchemy chips.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -23,18 +23,18 @@
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Notes :
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* This file must ONLY be built when CONFIG_GPIOLIB=y and
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* CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail!
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* au1000 SoC have only one GPIO block : GPIO1
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* Au1100, Au15x0, Au12x0 have a second one : GPIO2
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/platform_device.h>
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#include <linux/gpio.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/gpio.h>
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#include <asm/mach-au1x00/gpio-au1000.h>
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static int gpio2_get(struct gpio_chip *chip, unsigned offset)
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{
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@ -115,12 +115,19 @@ struct gpio_chip alchemy_gpio_chip[] = {
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},
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};
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static int __init alchemy_gpiolib_init(void)
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static int __init alchemy_gpiochip_init(void)
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{
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gpiochip_add(&alchemy_gpio_chip[0]);
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if (alchemy_get_cputype() != ALCHEMY_CPU_AU1000)
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gpiochip_add(&alchemy_gpio_chip[1]);
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int ret = 0;
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return 0;
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switch (alchemy_get_cputype()) {
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case ALCHEMY_CPU_AU1000:
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ret = gpiochip_add(&alchemy_gpio_chip[0]);
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break;
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case ALCHEMY_CPU_AU1500...ALCHEMY_CPU_AU1200:
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ret = gpiochip_add(&alchemy_gpio_chip[0]);
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ret |= gpiochip_add(&alchemy_gpio_chip[1]);
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break;
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}
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return ret;
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}
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arch_initcall(alchemy_gpiolib_init);
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arch_initcall(alchemy_gpiochip_init);
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@ -347,17 +347,6 @@ static inline int alchemy_gpio2_to_irq(int gpio)
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/**********************************************************************/
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/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
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* SYS_PININPUTEN is written to at least once. On Au1550/Au1200 this
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* register enables use of GPIOs as wake source.
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*/
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static inline void alchemy_gpio1_input_enable(void)
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{
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void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
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__raw_writel(0, base + SYS_PININPUTEN); /* the write op is key */
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wmb();
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}
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/* GPIO2 shared interrupts and control */
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static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
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@ -561,6 +550,7 @@ static inline int alchemy_irq_to_gpio(int irq)
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#ifndef CONFIG_GPIOLIB
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#ifdef CONFIG_ALCHEMY_GPIOINT_AU1000
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#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
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@ -665,24 +655,7 @@ static inline void gpio_unexport(unsigned gpio)
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#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
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#else /* CONFIG GPIOLIB */
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/* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
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#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */
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/* get everything through gpiolib */
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#define gpio_to_irq __gpio_to_irq
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#define gpio_get_value __gpio_get_value
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#define gpio_set_value __gpio_set_value
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#define gpio_cansleep __gpio_cansleep
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#define irq_to_gpio alchemy_irq_to_gpio
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#include <asm-generic/gpio.h>
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#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
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#endif /* CONFIG_ALCHEMY_GPIOINT_AU1000 */
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#endif /* !CONFIG_GPIOLIB */
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@ -1,10 +1,83 @@
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/*
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* Alchemy GPIO support.
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*
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* With CONFIG_GPIOLIB=y different types of on-chip GPIO can be supported within
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* the same kernel image.
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* With CONFIG_GPIOLIB=n, your board must select ALCHEMY_GPIOINT_AU1XXX for the
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* appropriate CPU type (AU1000 currently).
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*/
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#ifndef _ALCHEMY_GPIO_H_
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#define _ALCHEMY_GPIO_H_
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#if defined(CONFIG_ALCHEMY_GPIOINT_AU1000)
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/gpio-au1000.h>
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#endif
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/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
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* SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this
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* register enables use of GPIOs as wake source.
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*/
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static inline void alchemy_gpio1_input_enable(void)
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{
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void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
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__raw_writel(0, base + 0x110); /* the write op is key */
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wmb();
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}
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/* Linux gpio framework integration.
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*
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* 4 use cases of Alchemy GPIOS:
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*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
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* Board must register gpiochips.
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*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
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* A gpiochip for the 75 GPIOs is registered.
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*
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*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
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* the boards' gpio.h must provide the linux gpio wrapper functions,
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*
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*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
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* inlinable gpio functions are provided which enable access to the
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* Au1300 gpios only by using the numbers straight out of the data-
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* sheets.
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* Cases 1 and 3 are intended for boards which want to provide their own
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* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
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* which are in part provided by spare Au1300 GPIO pins and in part by
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* an external FPGA but you still want them to be accssible in linux
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* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
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* as required).
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*/
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#ifdef CONFIG_GPIOLIB
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/* wraps the cpu-dependent irq_to_gpio functions */
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/* FIXME: gpiolib needs an irq_to_gpio hook */
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static inline int __au_irq_to_gpio(unsigned int irq)
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{
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switch (alchemy_get_cputype()) {
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case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
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return alchemy_irq_to_gpio(irq);
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}
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return -EINVAL;
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}
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/* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
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#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */
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/* get everything through gpiolib */
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#define gpio_to_irq __gpio_to_irq
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#define gpio_get_value __gpio_get_value
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#define gpio_set_value __gpio_set_value
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#define gpio_cansleep __gpio_cansleep
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#define irq_to_gpio __au_irq_to_gpio
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#include <asm-generic/gpio.h>
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#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
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#endif /* CONFIG_GPIOLIB */
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#endif /* _ALCHEMY_GPIO_H_ */
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