forked from Minki/linux
MIPS: Alchemy: support multiple GPIO styles in one kernel
For GPIOLIB=y decide at runtime which gpiochips to register; in the GPIOLIB=n case, the gpio headers need to be reshuffled a bit to make multiple implementations coexist peacefully. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2679/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss
Ralf Baechle
parent
2e8fd2e5ef
commit
ce1d43b9a9
@ -12,9 +12,7 @@ obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o
|
||||
|
||||
# optional gpiolib support
|
||||
ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
|
||||
ifeq ($(CONFIG_GPIOLIB),y)
|
||||
obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += gpiolib-au1000.o
|
||||
endif
|
||||
obj-$(CONFIG_GPIOLIB) += gpiolib.o
|
||||
endif
|
||||
|
||||
obj-$(CONFIG_PCI) += pci.o
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
|
||||
* GPIOLIB support for Au1000, Au1500, Au1100, Au1550 and Au12x0.
|
||||
* GPIOLIB support for Alchemy chips.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
@ -23,18 +23,18 @@
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
* Notes :
|
||||
* au1000 SoC have only one GPIO block : GPIO1
|
||||
* Au1100, Au15x0, Au12x0 have a second one : GPIO2
|
||||
* This file must ONLY be built when CONFIG_GPIOLIB=y and
|
||||
* CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail!
|
||||
* au1000 SoC have only one GPIO block : GPIO1
|
||||
* Au1100, Au15x0, Au12x0 have a second one : GPIO2
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include <asm/mach-au1x00/au1000.h>
|
||||
#include <asm/mach-au1x00/gpio.h>
|
||||
#include <asm/mach-au1x00/gpio-au1000.h>
|
||||
|
||||
static int gpio2_get(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
@ -115,12 +115,19 @@ struct gpio_chip alchemy_gpio_chip[] = {
|
||||
},
|
||||
};
|
||||
|
||||
static int __init alchemy_gpiolib_init(void)
|
||||
static int __init alchemy_gpiochip_init(void)
|
||||
{
|
||||
gpiochip_add(&alchemy_gpio_chip[0]);
|
||||
if (alchemy_get_cputype() != ALCHEMY_CPU_AU1000)
|
||||
gpiochip_add(&alchemy_gpio_chip[1]);
|
||||
int ret = 0;
|
||||
|
||||
return 0;
|
||||
switch (alchemy_get_cputype()) {
|
||||
case ALCHEMY_CPU_AU1000:
|
||||
ret = gpiochip_add(&alchemy_gpio_chip[0]);
|
||||
break;
|
||||
case ALCHEMY_CPU_AU1500...ALCHEMY_CPU_AU1200:
|
||||
ret = gpiochip_add(&alchemy_gpio_chip[0]);
|
||||
ret |= gpiochip_add(&alchemy_gpio_chip[1]);
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
arch_initcall(alchemy_gpiolib_init);
|
||||
arch_initcall(alchemy_gpiochip_init);
|
||||
@ -347,17 +347,6 @@ static inline int alchemy_gpio2_to_irq(int gpio)
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
|
||||
* SYS_PININPUTEN is written to at least once. On Au1550/Au1200 this
|
||||
* register enables use of GPIOs as wake source.
|
||||
*/
|
||||
static inline void alchemy_gpio1_input_enable(void)
|
||||
{
|
||||
void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
|
||||
__raw_writel(0, base + SYS_PININPUTEN); /* the write op is key */
|
||||
wmb();
|
||||
}
|
||||
|
||||
/* GPIO2 shared interrupts and control */
|
||||
|
||||
static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
|
||||
@ -561,6 +550,7 @@ static inline int alchemy_irq_to_gpio(int irq)
|
||||
|
||||
#ifndef CONFIG_GPIOLIB
|
||||
|
||||
#ifdef CONFIG_ALCHEMY_GPIOINT_AU1000
|
||||
|
||||
#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
|
||||
|
||||
@ -665,24 +655,7 @@ static inline void gpio_unexport(unsigned gpio)
|
||||
|
||||
#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
|
||||
|
||||
|
||||
#else /* CONFIG GPIOLIB */
|
||||
|
||||
|
||||
/* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
|
||||
#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */
|
||||
|
||||
/* get everything through gpiolib */
|
||||
#define gpio_to_irq __gpio_to_irq
|
||||
#define gpio_get_value __gpio_get_value
|
||||
#define gpio_set_value __gpio_set_value
|
||||
#define gpio_cansleep __gpio_cansleep
|
||||
#define irq_to_gpio alchemy_irq_to_gpio
|
||||
|
||||
#include <asm-generic/gpio.h>
|
||||
|
||||
#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
|
||||
|
||||
#endif /* CONFIG_ALCHEMY_GPIOINT_AU1000 */
|
||||
|
||||
#endif /* !CONFIG_GPIOLIB */
|
||||
|
||||
|
||||
@ -1,10 +1,83 @@
|
||||
/*
|
||||
* Alchemy GPIO support.
|
||||
*
|
||||
* With CONFIG_GPIOLIB=y different types of on-chip GPIO can be supported within
|
||||
* the same kernel image.
|
||||
* With CONFIG_GPIOLIB=n, your board must select ALCHEMY_GPIOINT_AU1XXX for the
|
||||
* appropriate CPU type (AU1000 currently).
|
||||
*/
|
||||
|
||||
#ifndef _ALCHEMY_GPIO_H_
|
||||
#define _ALCHEMY_GPIO_H_
|
||||
|
||||
#if defined(CONFIG_ALCHEMY_GPIOINT_AU1000)
|
||||
|
||||
#include <asm/mach-au1x00/au1000.h>
|
||||
#include <asm/mach-au1x00/gpio-au1000.h>
|
||||
|
||||
#endif
|
||||
/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
|
||||
* SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this
|
||||
* register enables use of GPIOs as wake source.
|
||||
*/
|
||||
static inline void alchemy_gpio1_input_enable(void)
|
||||
{
|
||||
void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
|
||||
__raw_writel(0, base + 0x110); /* the write op is key */
|
||||
wmb();
|
||||
}
|
||||
|
||||
|
||||
/* Linux gpio framework integration.
|
||||
*
|
||||
* 4 use cases of Alchemy GPIOS:
|
||||
*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
|
||||
* Board must register gpiochips.
|
||||
*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
|
||||
* A gpiochip for the 75 GPIOs is registered.
|
||||
*
|
||||
*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
|
||||
* the boards' gpio.h must provide the linux gpio wrapper functions,
|
||||
*
|
||||
*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
|
||||
* inlinable gpio functions are provided which enable access to the
|
||||
* Au1300 gpios only by using the numbers straight out of the data-
|
||||
* sheets.
|
||||
|
||||
* Cases 1 and 3 are intended for boards which want to provide their own
|
||||
* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
|
||||
* which are in part provided by spare Au1300 GPIO pins and in part by
|
||||
* an external FPGA but you still want them to be accssible in linux
|
||||
* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
|
||||
* as required).
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_GPIOLIB
|
||||
|
||||
/* wraps the cpu-dependent irq_to_gpio functions */
|
||||
/* FIXME: gpiolib needs an irq_to_gpio hook */
|
||||
static inline int __au_irq_to_gpio(unsigned int irq)
|
||||
{
|
||||
switch (alchemy_get_cputype()) {
|
||||
case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
|
||||
return alchemy_irq_to_gpio(irq);
|
||||
}
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
||||
/* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
|
||||
#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */
|
||||
|
||||
/* get everything through gpiolib */
|
||||
#define gpio_to_irq __gpio_to_irq
|
||||
#define gpio_get_value __gpio_get_value
|
||||
#define gpio_set_value __gpio_set_value
|
||||
#define gpio_cansleep __gpio_cansleep
|
||||
#define irq_to_gpio __au_irq_to_gpio
|
||||
|
||||
#include <asm-generic/gpio.h>
|
||||
|
||||
#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
|
||||
|
||||
|
||||
#endif /* CONFIG_GPIOLIB */
|
||||
|
||||
#endif /* _ALCHEMY_GPIO_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user