drm/radeon/dce8: add support for display watermark setup
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@@ -259,6 +259,17 @@
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#define SDMA0 (1 << 10)
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#define SDMA1 (1 << 11)
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/* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */
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#define LB_MEMORY_CTRL 0x6b04
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#define LB_MEMORY_SIZE(x) ((x) << 0)
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#define LB_MEMORY_CONFIG(x) ((x) << 20)
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#define DPG_WATERMARK_MASK_CONTROL 0x6cc8
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# define LATENCY_WATERMARK_MASK(x) ((x) << 8)
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#define DPG_PIPE_LATENCY_CONTROL 0x6ccc
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# define LATENCY_LOW_WATERMARK(x) ((x) << 0)
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# define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
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/* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */
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#define LB_VLINE_STATUS 0x6b24
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# define VLINE_OCCURRED (1 << 0)
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