forked from Minki/linux
drm/amdgpu: add vcn decode ring type and functions
Add the ring function callbacks for the decode ring. Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Leo Liu
Alex Deucher
parent
a4bf608be5
commit
cca69fe8ff
@ -47,7 +47,8 @@ enum amdgpu_ring_type {
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AMDGPU_RING_TYPE_UVD,
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AMDGPU_RING_TYPE_VCE,
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AMDGPU_RING_TYPE_KIQ,
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AMDGPU_RING_TYPE_UVD_ENC
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AMDGPU_RING_TYPE_UVD_ENC,
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AMDGPU_RING_TYPE_VCN_DEC
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};
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struct amdgpu_device;
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@ -37,6 +37,7 @@
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static int vcn_v1_0_start(struct amdgpu_device *adev);
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static int vcn_v1_0_stop(struct amdgpu_device *adev);
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static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
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/**
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* vcn_v1_0_early_init - set function pointers
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@ -47,6 +48,10 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev);
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*/
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static int vcn_v1_0_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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vcn_v1_0_set_dec_ring_funcs(adev);
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return 0;
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}
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@ -439,6 +444,236 @@ static int vcn_v1_0_set_clockgating_state(void *handle,
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return 0;
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}
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/**
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* vcn_v1_0_dec_ring_get_rptr - get read pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Returns the current hardware read pointer
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*/
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static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR));
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}
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/**
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* vcn_v1_0_dec_ring_get_wptr - get write pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Returns the current hardware write pointer
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*/
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static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR));
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}
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/**
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* vcn_v1_0_dec_ring_set_wptr - set write pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Commits the write pointer to the hardware
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*/
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static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR), lower_32_bits(ring->wptr));
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}
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/**
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* vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command
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*
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* @ring: amdgpu_ring pointer
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* @fence: fence to emit
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*
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* Write a fence and a trap command to the ring.
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*/
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static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
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unsigned flags)
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{
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WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
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amdgpu_ring_write(ring, seq);
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
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amdgpu_ring_write(ring, addr & 0xffffffff);
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
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amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
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amdgpu_ring_write(ring, 0);
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
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amdgpu_ring_write(ring, 0);
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
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amdgpu_ring_write(ring, 0);
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
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amdgpu_ring_write(ring, 2);
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}
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/**
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* vcn_v1_0_dec_ring_hdp_invalidate - emit an hdp invalidate
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*
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* @ring: amdgpu_ring pointer
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*
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* Emits an hdp invalidate.
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*/
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static void vcn_v1_0_dec_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
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{
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amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 0));
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amdgpu_ring_write(ring, 1);
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}
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/**
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* vcn_v1_0_dec_ring_test_ring - register write test
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*
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* @ring: amdgpu_ring pointer
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*
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* Test if we can successfully write to the context register
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*/
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static int vcn_v1_0_dec_ring_test_ring(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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uint32_t tmp = 0;
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unsigned i;
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int r;
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD);
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r = amdgpu_ring_alloc(ring, 3);
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if (r) {
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DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
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ring->idx, r);
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return r;
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}
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
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amdgpu_ring_write(ring, 0xDEADBEEF);
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amdgpu_ring_commit(ring);
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for (i = 0; i < adev->usec_timeout; i++) {
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tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID));
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if (tmp == 0xDEADBEEF)
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break;
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DRM_UDELAY(1);
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}
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if (i < adev->usec_timeout) {
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DRM_INFO("ring test on %d succeeded in %d usecs\n",
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ring->idx, i);
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} else {
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DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
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ring->idx, tmp);
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r = -EINVAL;
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}
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return r;
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}
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/**
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* vcn_v1_0_dec_ring_emit_ib - execute indirect buffer
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*
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* @ring: amdgpu_ring pointer
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* @ib: indirect buffer to execute
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*
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* Write ring commands to execute the indirect buffer
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*/
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static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
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struct amdgpu_ib *ib,
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unsigned vm_id, bool ctx_switch)
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{
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
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amdgpu_ring_write(ring, vm_id);
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
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amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
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amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
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amdgpu_ring_write(ring, ib->length_dw);
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}
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static void vcn_v1_0_dec_vm_reg_write(struct amdgpu_ring *ring,
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uint32_t data0, uint32_t data1)
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{
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
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amdgpu_ring_write(ring, data0);
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
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amdgpu_ring_write(ring, data1);
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
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amdgpu_ring_write(ring, 8);
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}
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static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring,
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uint32_t data0, uint32_t data1, uint32_t mask)
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{
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
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amdgpu_ring_write(ring, data0);
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
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amdgpu_ring_write(ring, data1);
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
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amdgpu_ring_write(ring, mask);
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amdgpu_ring_write(ring,
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PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
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amdgpu_ring_write(ring, 12);
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}
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static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
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unsigned vm_id, uint64_t pd_addr)
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{
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struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
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uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
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uint32_t data0, data1, mask;
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unsigned eng = ring->vm_inv_eng;
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pd_addr = pd_addr | 0x1; /* valid bit */
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/* now only use physical base address of PDE and valid */
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BUG_ON(pd_addr & 0xFFFF00000000003EULL);
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data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2;
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data1 = upper_32_bits(pd_addr);
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vcn_v1_0_dec_vm_reg_write(ring, data0, data1);
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data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
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data1 = lower_32_bits(pd_addr);
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vcn_v1_0_dec_vm_reg_write(ring, data0, data1);
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data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
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data1 = lower_32_bits(pd_addr);
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mask = 0xffffffff;
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vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask);
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/* flush TLB */
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data0 = (hub->vm_inv_eng0_req + eng) << 2;
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data1 = req;
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vcn_v1_0_dec_vm_reg_write(ring, data0, data1);
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/* wait for flush */
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data0 = (hub->vm_inv_eng0_ack + eng) << 2;
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data1 = 1 << vm_id;
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mask = 1 << vm_id;
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vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask);
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}
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static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
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.name = "vcn_v1_0",
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.early_init = vcn_v1_0_early_init,
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@ -458,3 +693,34 @@ static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
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.set_clockgating_state = vcn_v1_0_set_clockgating_state,
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.set_powergating_state = NULL /* vcn_v1_0_set_powergating_state */,
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};
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static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
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.type = AMDGPU_RING_TYPE_VCN_DEC,
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.align_mask = 0xf,
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.nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),
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.support_64bit_ptrs = false,
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.get_rptr = vcn_v1_0_dec_ring_get_rptr,
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.get_wptr = vcn_v1_0_dec_ring_get_wptr,
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.set_wptr = vcn_v1_0_dec_ring_set_wptr,
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.emit_frame_size =
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2 + /* vcn_v1_0_dec_ring_emit_hdp_invalidate */
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34 * AMDGPU_MAX_VMHUBS + /* vcn_v1_0_dec_ring_emit_vm_flush */
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14 + 14, /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
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.emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
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.emit_ib = vcn_v1_0_dec_ring_emit_ib,
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.emit_fence = vcn_v1_0_dec_ring_emit_fence,
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.emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
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.emit_hdp_invalidate = vcn_v1_0_dec_ring_emit_hdp_invalidate,
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.test_ring = vcn_v1_0_dec_ring_test_ring,
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.test_ib = amdgpu_vcn_dec_ring_test_ib,
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.insert_nop = amdgpu_ring_insert_nop,
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.pad_ib = amdgpu_ring_generic_pad_ib,
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.begin_use = amdgpu_vcn_ring_begin_use,
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.end_use = amdgpu_vcn_ring_end_use,
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};
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static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
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{
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adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
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DRM_INFO("VCN decode is enabled in VM mode\n");
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}
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