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pinctrl: sunxi: Support I/O bias voltage setting on H6

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H6 SoC has a "pio group withstand voltage mode" register (datasheet
description), that needs to be used to select either 1.8V or 3.3V I/O mode,
based on what voltage is powering the respective pin banks and is thus used
for I/O signals.

Add support for configuring this register according to the voltage of the
pin bank regulator (if enabled).

This is similar to the support for I/O bias voltage setting patch for A80
and the same concerns apply. See:

  commit 402bfb3c13 ("Support I/O bias voltage setting on A80")

Signed-off-by: Ondrej Jirman <megous@megous.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Ondrej Jirman 2019-04-13 18:54:13 +02:00 committed by Linus Walleij
parent f727534572
commit cc62383fce
3 changed files with 19 additions and 0 deletions
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1
drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
View File

@ -591,6 +591,7 @@ static const struct sunxi_pinctrl_desc h6_pinctrl_data = {
.irq_banks = 4, .irq_banks = 4,
.irq_bank_map = h6_irq_bank_map, .irq_bank_map = h6_irq_bank_map,
.irq_read_needs_mux = true, .irq_read_needs_mux = true,
.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
}; };
static int h6_pinctrl_probe(struct platform_device *pdev) static int h6_pinctrl_probe(struct platform_device *pdev)

11
drivers/pinctrl/sunxi/pinctrl-sunxi.c
View File

@ -614,6 +614,8 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
unsigned pin, unsigned pin,
struct regulator *supply) struct regulator *supply)
{ {
unsigned short bank = pin / PINS_PER_BANK;
unsigned long flags;
u32 val, reg; u32 val, reg;
int uV; int uV;
@ -651,6 +653,15 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
reg &= ~IO_BIAS_MASK; reg &= ~IO_BIAS_MASK;
writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
return 0; return 0;
case BIAS_VOLTAGE_PIO_POW_MODE_SEL:
val = uV <= 1800000 ? 1 : 0;
raw_spin_lock_irqsave(&pctl->lock, flags);
reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG);
reg &= ~(1 << bank);
writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG);
raw_spin_unlock_irqrestore(&pctl->lock, flags);
return 0;
default: default:
return -EINVAL; return -EINVAL;
} }

7
drivers/pinctrl/sunxi/pinctrl-sunxi.h
View File

@ -95,6 +95,8 @@
#define PINCTRL_SUN7I_A20 BIT(7) #define PINCTRL_SUN7I_A20 BIT(7)
#define PINCTRL_SUN8I_R40 BIT(8) #define PINCTRL_SUN8I_R40 BIT(8)
#define PIO_POW_MOD_SEL_REG 0x340
enum sunxi_desc_bias_voltage { enum sunxi_desc_bias_voltage {
BIAS_VOLTAGE_NONE, BIAS_VOLTAGE_NONE,
/* /*
@ -102,6 +104,11 @@ enum sunxi_desc_bias_voltage {
* Pn_GRP_CONFIG registers, as seen on A80 SoC. * Pn_GRP_CONFIG registers, as seen on A80 SoC.
*/ */
BIAS_VOLTAGE_GRP_CONFIG, BIAS_VOLTAGE_GRP_CONFIG,
/*
* Bias voltage is set through PIO_POW_MOD_SEL_REG
* register, as seen on H6 SoC, for example.
*/
BIAS_VOLTAGE_PIO_POW_MODE_SEL,
}; };
struct sunxi_desc_function { struct sunxi_desc_function {