forked from Minki/linux
habanalabs: clear msg_to_cpu_reg to avoid misread after reset
For some ASICs, the f/w reads the msg_to_cpu_reg value after reset, and for some it doesn't. Therefore, to be sure f/w doesn't read a wrong value after reset, we need to clear this register before the reset occurs. Signed-off-by: Koby Elbaz <kelbaz@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
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@ -667,17 +667,15 @@ int hl_fw_cpucp_info_get(struct hl_device *hdev,
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hdev->event_queue.check_eqe_index = false;
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/* Read FW application security bits again */
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if (hdev->asic_prop.fw_cpu_boot_dev_sts0_valid) {
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hdev->asic_prop.fw_app_cpu_boot_dev_sts0 =
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RREG32(sts_boot_dev_sts0_reg);
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if (hdev->asic_prop.fw_app_cpu_boot_dev_sts0 &
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if (prop->fw_cpu_boot_dev_sts0_valid) {
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prop->fw_app_cpu_boot_dev_sts0 = RREG32(sts_boot_dev_sts0_reg);
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if (prop->fw_app_cpu_boot_dev_sts0 &
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CPU_BOOT_DEV_STS0_EQ_INDEX_EN)
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hdev->event_queue.check_eqe_index = true;
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}
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if (hdev->asic_prop.fw_cpu_boot_dev_sts1_valid)
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hdev->asic_prop.fw_app_cpu_boot_dev_sts1 =
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RREG32(sts_boot_dev_sts1_reg);
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if (prop->fw_cpu_boot_dev_sts1_valid)
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prop->fw_app_cpu_boot_dev_sts1 = RREG32(sts_boot_dev_sts1_reg);
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out:
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hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev,
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@ -1012,6 +1010,11 @@ void hl_fw_ask_halt_machine_without_linux(struct hl_device *hdev)
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} else {
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WREG32(static_loader->kmd_msg_to_cpu_reg, KMD_MSG_GOTO_WFE);
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msleep(static_loader->cpu_reset_wait_msec);
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/* Must clear this register in order to prevent preboot
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* from reading WFE after reboot
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*/
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WREG32(static_loader->kmd_msg_to_cpu_reg, KMD_MSG_NA);
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}
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hdev->device_cpu_is_halted = true;
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@ -1242,11 +1245,6 @@ static void hl_fw_preboot_update_state(struct hl_device *hdev)
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* b. Check whether hard reset is done by boot cpu
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* 3. FW application - a. Fetch fw application security status
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* b. Check whether hard reset is done by fw app
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*
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* Preboot:
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* Check security status bit (CPU_BOOT_DEV_STS0_ENABLED). If set, then-
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* check security enabled bit (CPU_BOOT_DEV_STS0_SECURITY_EN)
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* If set, then mark GIC controller to be disabled.
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*/
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prop->hard_reset_done_by_fw =
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!!(cpu_boot_dev_sts0 & CPU_BOOT_DEV_STS0_FW_HARD_RST_EN);
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@ -2126,8 +2124,7 @@ static void hl_fw_linux_update_state(struct hl_device *hdev,
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/* Read FW application security bits */
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if (prop->fw_cpu_boot_dev_sts0_valid) {
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prop->fw_app_cpu_boot_dev_sts0 =
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RREG32(cpu_boot_dev_sts0_reg);
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prop->fw_app_cpu_boot_dev_sts0 = RREG32(cpu_boot_dev_sts0_reg);
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if (prop->fw_app_cpu_boot_dev_sts0 &
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CPU_BOOT_DEV_STS0_FW_HARD_RST_EN)
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@ -2147,8 +2144,7 @@ static void hl_fw_linux_update_state(struct hl_device *hdev,
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}
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if (prop->fw_cpu_boot_dev_sts1_valid) {
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prop->fw_app_cpu_boot_dev_sts1 =
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RREG32(cpu_boot_dev_sts1_reg);
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prop->fw_app_cpu_boot_dev_sts1 = RREG32(cpu_boot_dev_sts1_reg);
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dev_dbg(hdev->dev,
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"Firmware application CPU status1 %#x\n",
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