Merge tag 'mips_4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Paul Burton: - kexec support for the generic MIPS platform when running on a CPU including the MIPS Coherence Manager & related hardware. - Improvements to the definition of memory barriers used around MMIO accesses, and fixes in their use. - Switch to CONFIG_NO_BOOTMEM from Mike Rapoport, finally dropping reliance on the old bootmem code. - A number of fixes & improvements for Loongson 3 systems. - DT & config updates for the Microsemi Ocelot platform. - Workaround to enable USB power on the Netgear WNDR3400v3. - Various cleanups & fixes. * tag 'mips_4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (51 commits) MIPS: Cleanup DSP ASE detection MIPS: dts: Change upper case to lower case MIPS: generic: Add Network, SPI and I2C to ocelot_defconfig MIPS: Loongson-3: Fix BRIDGE irq delivery problem MIPS: Loongson-3: Fix CPU UART irq delivery problem MIPS: Remove unused PREF, PREFE & PREFX macros MIPS: lib: Use kernel_pref & user_pref in memcpy() MIPS: Remove unused CAT macro MIPS: Add kernel_pref & user_pref helpers MIPS: Remove unused TTABLE macro MIPS: Remove unused PIC macros MIPS: Remove unused MOVN & MOVZ macros MIPS: Provide actually relaxed MMIO accessors MIPS: Enforce strong ordering for MMIO accessors MIPS: Correct `mmiowb' barrier for `wbflush' platforms MIPS: Define MMIO ordering barriers MIPS: mscc: add PCB120 to the ocelot fitImage MIPS: mscc: add DT for Ocelot PCB120 MIPS: memset: Limit excessive `noreorder' assembly mode use MIPS: memset: Fix CPU_DADDI_WORKAROUNDS `small_fixup' regression ...
This commit is contained in:
Linus Torvalds
@@ -10,12 +10,12 @@
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};
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};
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biu@1F800000 {
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biu@1f800000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,biu", "simple-bus";
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reg = <0x1F800000 0x800000>;
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ranges = <0x0 0x1F800000 0x7FFFFF>;
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reg = <0x1f800000 0x800000>;
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ranges = <0x0 0x1f800000 0x7fffff>;
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icu0: icu@80200 {
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#interrupt-cells = <1>;
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@@ -24,18 +24,18 @@
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reg = <0x80200 0x120>;
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};
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watchdog@803F0 {
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watchdog@803f0 {
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compatible = "lantiq,wdt";
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reg = <0x803F0 0x10>;
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reg = <0x803f0 0x10>;
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};
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};
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sram@1F000000 {
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sram@1f000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,sram";
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reg = <0x1F000000 0x800000>;
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ranges = <0x0 0x1F000000 0x7FFFFF>;
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reg = <0x1f000000 0x800000>;
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ranges = <0x0 0x1f000000 0x7fffff>;
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eiu0: eiu@101000 {
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#interrupt-cells = <1>;
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@@ -66,41 +66,41 @@
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,fpi", "simple-bus";
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ranges = <0x0 0x10000000 0xEEFFFFF>;
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reg = <0x10000000 0xEF00000>;
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ranges = <0x0 0x10000000 0xeefffff>;
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reg = <0x10000000 0xef00000>;
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gptu@E100A00 {
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gptu@e100a00 {
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compatible = "lantiq,gptu-xway";
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reg = <0xE100A00 0x100>;
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reg = <0xe100a00 0x100>;
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};
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serial@E100C00 {
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serial@e100c00 {
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compatible = "lantiq,asc";
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reg = <0xE100C00 0x400>;
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reg = <0xe100c00 0x400>;
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interrupt-parent = <&icu0>;
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interrupts = <112 113 114>;
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};
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dma0: dma@E104100 {
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dma0: dma@e104100 {
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compatible = "lantiq,dma-xway";
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reg = <0xE104100 0x800>;
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reg = <0xe104100 0x800>;
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};
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ebu0: ebu@E105300 {
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ebu0: ebu@e105300 {
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compatible = "lantiq,ebu-xway";
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reg = <0xE105300 0x100>;
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reg = <0xe105300 0x100>;
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};
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pci0: pci@E105400 {
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pci0: pci@e105400 {
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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compatible = "lantiq,pci-xway";
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bus-range = <0x0 0x0>;
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ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
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0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */
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0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */
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reg = <0x7000000 0x8000 /* config space */
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0xE105400 0x400>; /* pci bridge */
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0xe105400 0x400>; /* pci bridge */
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};
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};
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};
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@@ -52,14 +52,14 @@
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};
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};
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gpio: pinmux@E100B10 {
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gpio: pinmux@e100b10 {
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compatible = "lantiq,danube-pinctrl";
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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#gpio-cells = <2>;
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gpio-controller;
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reg = <0xE100B10 0xA0>;
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reg = <0xe100b10 0xa0>;
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state_default: pinmux {
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stp {
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@@ -82,26 +82,26 @@
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};
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};
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etop@E180000 {
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etop@e180000 {
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compatible = "lantiq,etop-xway";
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reg = <0xE180000 0x40000>;
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reg = <0xe180000 0x40000>;
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interrupt-parent = <&icu0>;
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interrupts = <73 78>;
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phy-mode = "rmii";
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mac-address = [ 00 11 22 33 44 55 ];
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};
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stp0: stp@E100BB0 {
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stp0: stp@e100bb0 {
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#gpio-cells = <2>;
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compatible = "lantiq,gpio-stp-xway";
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gpio-controller;
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reg = <0xE100BB0 0x40>;
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reg = <0xe100bb0 0x40>;
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lantiq,shadow = <0xfff>;
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lantiq,groups = <0x3>;
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};
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pci@E105400 {
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pci@e105400 {
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lantiq,bus-clock = <33333333>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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@@ -1,3 +1,3 @@
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dtb-$(CONFIG_MSCC_OCELOT) += ocelot_pcb123.dtb
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dtb-$(CONFIG_MSCC_OCELOT) += ocelot_pcb123.dtb ocelot_pcb120.dtb
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obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
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@@ -78,6 +78,19 @@
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status = "disabled";
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};
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i2c: i2c@100400 {
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compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
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pinctrl-0 = <&i2c_pins>;
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pinctrl-names = "default";
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reg = <0x100400 0x100>, <0x198 0x8>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <8>;
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clocks = <&ahb_clk>;
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status = "disabled";
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};
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uart2: serial@100800 {
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pinctrl-0 = <&uart2_pins>;
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pinctrl-names = "default";
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@@ -182,6 +195,11 @@
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interrupts = <13>;
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#interrupt-cells = <2>;
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i2c_pins: i2c-pins {
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pins = "GPIO_16", "GPIO_17";
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function = "twi";
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};
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uart_pins: uart-pins {
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pins = "GPIO_6", "GPIO_7";
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function = "uart";
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@@ -196,6 +214,7 @@
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pins = "GPIO_14", "GPIO_15";
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function = "miim1";
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};
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};
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mdio0: mdio@107009c {
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107
arch/mips/boot/dts/mscc/ocelot_pcb120.dts
Normal file
107
arch/mips/boot/dts/mscc/ocelot_pcb120.dts
Normal file
@@ -0,0 +1,107 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2017 Microsemi Corporation */
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/phy/phy-ocelot-serdes.h>
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#include "ocelot.dtsi"
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/ {
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compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0e000000>;
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};
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};
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&gpio {
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phy_int_pins: phy_int_pins {
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pins = "GPIO_4";
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function = "gpio";
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};
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};
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&mdio0 {
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status = "okay";
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};
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&mdio1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&miim1>, <&phy_int_pins>;
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phy7: ethernet-phy@0 {
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reg = <0>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gpio>;
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};
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phy6: ethernet-phy@1 {
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reg = <1>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gpio>;
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};
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phy5: ethernet-phy@2 {
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reg = <2>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gpio>;
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};
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phy4: ethernet-phy@3 {
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reg = <3>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gpio>;
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};
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};
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&port0 {
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phy-handle = <&phy0>;
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};
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&port1 {
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phy-handle = <&phy1>;
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};
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&port2 {
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phy-handle = <&phy2>;
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};
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&port3 {
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phy-handle = <&phy3>;
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};
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&port4 {
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phy-handle = <&phy7>;
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phy-mode = "sgmii";
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phys = <&serdes 4 SERDES1G(2)>;
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};
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&port5 {
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phy-handle = <&phy4>;
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phy-mode = "sgmii";
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phys = <&serdes 5 SERDES1G(5)>;
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};
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&port6 {
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phy-handle = <&phy6>;
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phy-mode = "sgmii";
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phys = <&serdes 6 SERDES1G(3)>;
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};
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&port9 {
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phy-handle = <&phy5>;
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phy-mode = "sgmii";
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phys = <&serdes 9 SERDES1G(4)>;
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};
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&uart0 {
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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@@ -36,6 +36,12 @@
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};
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};
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&i2c {
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clock-frequency = <100000>;
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i2c-sda-hold-time-ns = <300>;
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status = "okay";
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};
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&mdio0 {
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status = "okay";
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};
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