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drm/i915: Record platform specific ppGTT size in intel_device_info

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As the maximum addressable bits is determined by platform, record that
information in our static chipset tables. This has the advantage of
being clearly recorded in our capability dumps for dmesg, debugfs and
error states.

Based on a patch by Bob Paauwe.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Bob Paauwe <bob.j.paauwe@intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190314223839.28258-2-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
2019-03-14 22:38:36 +00:00
parent ca6ac684de
commit cbecbccaa1
6 changed files with 22 additions and 17 deletions
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6
drivers/gpu/drm/i915/intel_device_info.h
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@@ -76,7 +76,7 @@ enum intel_platform {
INTEL_MAX_PLATFORMS
};
enum intel_ppgtt {
enum intel_ppgtt_type {
INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
@@ -162,7 +162,9 @@ struct intel_device_info {
enum intel_platform platform;
u32 platform_mask;
enum intel_ppgtt ppgtt;
enum intel_ppgtt_type ppgtt_type;
unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
unsigned int page_sizes; /* page sizes supported by the HW */
u32 display_mmio_offset;