ARMv8 Vexpress/Juno DT updates for v4.10
1. Addition of SMMU(MMU-401) device nodes mainly to assist other
developments and testing
2. Addition of CPU dmips/capacity information on all the Juno boards
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCAAGBQJYEyVrAAoJEABBurwxfuKYTU0P/3cQeB1rzmoowQwInGL8Qr/u
CYqB8eQ1j8w4m0bgCkeoszqHeH5XKeRGneE+YZtQ07fz82iaeJ9BqvAos9cWsy5a
WEjJEDKyicreZpMBK3hUhqlNSGWJZXa/E+O9IbnmFsoYiNon0mE1Fu6JOFTxzR42
3OrQPUHE5mv8MthTwnqUTM2LvgovYMNV9TJ1kdCysuyj0BfAUTmwgNcMO9BJEQku
fwtnCexO4RJqD37eflf4YpZRHg3+L5ylv81RJegE1aru+812c4S9za/cEMAPbKED
7Tw6whcEWhNFJizPsxrxcLI+afkdEFb+ahLhWzzrzDPMi6KUxAq+1haGbecIHOUt
hgNTOQ1bCXhC3plh+JwRrQI77eBBoncCwpRHacqoRFIlxi6zM3h5psc0NwjvNKQF
3WLMzgAjffF2JOKXjYG4S24rog6qVyj4N1JUQ8ieJyq/2ecV9UGHep4aCbzJiv5g
CWmKM1tCOmSKOHiN0SNtQFTt/9JdbRSwUtRvUeSeU9dshKQEmjfXAq0vNShhwR6r
NPv+8vuEMXS3NEJkgCikWdyNXq9E4O/nAQIXvF6DqgeXM2pvLouOFpPaXEVbv3SX
9VmLP6+M+CbEXYESCfLroBRCNQUCHt4ug40dA0V99+T11o0aTf7M0jWnkkEP3Tke
f2pSztRsFS0CLd1myYWU
=PFTb
-----END PGP SIGNATURE-----
Merge tag 'juno-dt-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt64
ARMv8 Vexpress/Juno DT updates for v4.10
1. Addition of SMMU(MMU-401) device nodes mainly to assist other
developments and testing
2. Addition of CPU dmips/capacity information on all the Juno boards
* tag 'juno-dt-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: add cpu capacity-dmips-mhz information to R2 boards
arm64: dts: juno: add cpu capacity-dmips-mhz information to R1 boards
arm64: dts: juno: add cpu capacity-dmips-mhz information to R0 boards
arm64: dts: juno: Add SMMUs device nodes
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
cbd8225981
@ -29,6 +29,28 @@
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clock-names = "apb_pclk";
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};
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smmu_pcie: iommu@2b500000 {
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compatible = "arm,mmu-401", "arm,smmu-v1";
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reg = <0x0 0x2b500000 0x0 0x10000>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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#global-interrupts = <1>;
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dma-coherent;
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status = "disabled";
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};
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smmu_etr: iommu@2b600000 {
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compatible = "arm,mmu-401", "arm,smmu-v1";
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reg = <0x0 0x2b600000 0x0 0x10000>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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#global-interrupts = <1>;
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dma-coherent;
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status = "disabled";
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};
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gic: interrupt-controller@2c010000 {
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compatible = "arm,gic-400", "arm,cortex-a15-gic";
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reg = <0x0 0x2c010000 0 0x1000>,
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@ -146,6 +168,7 @@
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etr@20070000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0 0x20070000 0 0x1000>;
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iommus = <&smmu_etr 0>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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@ -404,6 +427,8 @@
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<0 0 0 4 &gic 0 0 0 139 4>;
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msi-parent = <&v2m_0>;
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status = "disabled";
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iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
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iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
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};
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scpi {
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@ -484,6 +509,48 @@
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/include/ "juno-clocks.dtsi"
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smmu_dma: iommu@7fb00000 {
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compatible = "arm,mmu-401", "arm,smmu-v1";
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reg = <0x0 0x7fb00000 0x0 0x10000>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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#global-interrupts = <1>;
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dma-coherent;
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status = "disabled";
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};
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smmu_hdlcd1: iommu@7fb10000 {
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compatible = "arm,mmu-401", "arm,smmu-v1";
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reg = <0x0 0x7fb10000 0x0 0x10000>;
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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#global-interrupts = <1>;
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status = "disabled";
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};
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smmu_hdlcd0: iommu@7fb20000 {
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compatible = "arm,mmu-401", "arm,smmu-v1";
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reg = <0x0 0x7fb20000 0x0 0x10000>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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#global-interrupts = <1>;
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status = "disabled";
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};
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smmu_usb: iommu@7fb30000 {
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compatible = "arm,mmu-401", "arm,smmu-v1";
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reg = <0x0 0x7fb30000 0x0 0x10000>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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#global-interrupts = <1>;
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dma-coherent;
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status = "disabled";
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};
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dma@7ff00000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x0 0x7ff00000 0 0x1000>;
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@ -499,6 +566,15 @@
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&smmu_dma 0>,
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<&smmu_dma 1>,
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<&smmu_dma 2>,
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<&smmu_dma 3>,
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<&smmu_dma 4>,
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<&smmu_dma 5>,
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<&smmu_dma 6>,
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<&smmu_dma 7>,
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<&smmu_dma 8>;
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clocks = <&soc_faxiclk>;
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clock-names = "apb_pclk";
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};
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@ -507,6 +583,7 @@
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compatible = "arm,hdlcd";
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reg = <0 0x7ff50000 0 0x1000>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&smmu_hdlcd1 0>;
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clocks = <&scpi_clk 3>;
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clock-names = "pxlclk";
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@ -521,6 +598,7 @@
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compatible = "arm,hdlcd";
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reg = <0 0x7ff60000 0 0x1000>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&smmu_hdlcd0 0>;
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clocks = <&scpi_clk 3>;
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clock-names = "pxlclk";
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@ -574,6 +652,7 @@
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compatible = "generic-ohci";
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reg = <0x0 0x7ffb0000 0x0 0x10000>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&smmu_usb 0>;
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clocks = <&soc_usb48mhz>;
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};
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@ -581,6 +660,7 @@
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compatible = "generic-ehci";
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reg = <0x0 0x7ffc0000 0x0 0x10000>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&smmu_usb 0>;
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clocks = <&soc_usb48mhz>;
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};
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@ -90,6 +90,7 @@
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next-level-cache = <&A57_L2>;
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clocks = <&scpi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <1024>;
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};
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A57_1: cpu@1 {
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@ -100,6 +101,7 @@
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next-level-cache = <&A57_L2>;
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clocks = <&scpi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <1024>;
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};
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A53_0: cpu@100 {
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@ -110,6 +112,7 @@
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <578>;
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};
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A53_1: cpu@101 {
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@ -120,6 +123,7 @@
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <578>;
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};
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A53_2: cpu@102 {
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@ -130,6 +134,7 @@
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <578>;
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};
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A53_3: cpu@103 {
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@ -140,6 +145,7 @@
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <578>;
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};
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A57_L2: l2-cache0 {
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@ -90,6 +90,7 @@
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next-level-cache = <&A72_L2>;
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clocks = <&scpi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <1024>;
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};
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A72_1: cpu@1 {
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@ -100,6 +101,7 @@
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next-level-cache = <&A72_L2>;
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clocks = <&scpi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <1024>;
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};
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A53_0: cpu@100 {
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@ -110,6 +112,7 @@
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <485>;
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};
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A53_1: cpu@101 {
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@ -120,6 +123,7 @@
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <485>;
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};
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A53_2: cpu@102 {
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@ -130,6 +134,7 @@
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <485>;
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};
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A53_3: cpu@103 {
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@ -140,6 +145,7 @@
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <485>;
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};
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A72_L2: l2-cache0 {
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@ -90,6 +90,7 @@
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next-level-cache = <&A57_L2>;
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clocks = <&scpi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <1024>;
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};
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A57_1: cpu@1 {
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@ -100,6 +101,7 @@
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next-level-cache = <&A57_L2>;
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clocks = <&scpi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <1024>;
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};
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A53_0: cpu@100 {
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@ -110,6 +112,7 @@
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <578>;
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};
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A53_1: cpu@101 {
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@ -120,6 +123,7 @@
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <578>;
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};
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A53_2: cpu@102 {
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@ -130,6 +134,7 @@
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <578>;
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};
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A53_3: cpu@103 {
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@ -140,6 +145,7 @@
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <578>;
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};
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A57_L2: l2-cache0 {
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