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mlxsw: Fix naming convention of MFDE fields

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Currently, the MFDE register field names are using the convention:
reg_mfde_<NAME_OF_FIELD>, and do not consider the name of the MFDE
event.

Fix the field names so they fit the more accurate convention:
reg_mfde_<NAME_OF_EVENT>_<NAME_OF_FIELD>.

Signed-off-by: Danielle Ratson <danieller@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Danielle Ratson 2021-12-20 12:56:11 +02:00 committed by David S. Miller
parent 802d4d207e
commit cbbd5fff86
2 changed files with 12 additions and 15 deletions
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8
drivers/net/ethernet/mellanox/mlxsw/core.c
View File

@ -1801,20 +1801,20 @@ static int mlxsw_core_health_fw_fatal_dump(struct devlink_health_reporter *repor
return err;
if (event_id == MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO) {
val = mlxsw_reg_mfde_log_address_get(mfde_pl);
val = mlxsw_reg_mfde_crspace_to_log_address_get(mfde_pl);
err = devlink_fmsg_u32_pair_put(fmsg, "log_address", val);
if (err)
return err;
val = mlxsw_reg_mfde_log_id_get(mfde_pl);
val = mlxsw_reg_mfde_crspace_to_log_id_get(mfde_pl);
err = devlink_fmsg_u8_pair_put(fmsg, "log_irisc_id", val);
if (err)
return err;
val = mlxsw_reg_mfde_log_ip_get(mfde_pl);
val = mlxsw_reg_mfde_crspace_to_log_ip_get(mfde_pl);
err = devlink_fmsg_u64_pair_put(fmsg, "log_ip", val);
if (err)
return err;
} else if (event_id == MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP) {
val = mlxsw_reg_mfde_pipes_mask_get(mfde_pl);
val = mlxsw_reg_mfde_kvd_im_stop_pipes_mask_get(mfde_pl);
err = devlink_fmsg_u32_pair_put(fmsg, "pipes_mask", val);
if (err)
return err;

19
drivers/net/ethernet/mellanox/mlxsw/reg.h
View File

@ -11372,32 +11372,29 @@ MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2);
*/
MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16);
/* reg_mfde_log_address
/* reg_mfde_crspace_to_log_address
* crspace address accessed, which resulted in timeout.
* Valid in case event_id == MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO
* Access: RO
*/
MLXSW_ITEM32(reg, mfde, log_address, 0x10, 0, 32);
MLXSW_ITEM32(reg, mfde, crspace_to_log_address, 0x10, 0, 32);
/* reg_mfde_log_id
/* reg_mfde_crspace_to_log_id
* Which irisc triggered the timeout.
* Valid in case event_id == MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO
* Access: RO
*/
MLXSW_ITEM32(reg, mfde, log_id, 0x14, 0, 4);
MLXSW_ITEM32(reg, mfde, crspace_to_log_id, 0x14, 0, 4);
/* reg_mfde_log_ip
/* reg_mfde_crspace_to_log_ip
* IP (instruction pointer) that triggered the timeout.
* Valid in case event_id == MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO
* Access: RO
*/
MLXSW_ITEM64(reg, mfde, log_ip, 0x18, 0, 64);
MLXSW_ITEM64(reg, mfde, crspace_to_log_ip, 0x18, 0, 64);
/* reg_mfde_pipes_mask
/* reg_mfde_kvd_im_stop_pipes_mask
* Bit per kvh pipe.
* Access: RO
*/
MLXSW_ITEM32(reg, mfde, pipes_mask, 0x10, 0, 16);
MLXSW_ITEM32(reg, mfde, kvd_im_stop_pipes_mask, 0x10, 0, 16);
/* TNGCR - Tunneling NVE General Configuration Register
* ----------------------------------------------------