dt-bindings: Changes for v5.18-rc1
This contains additions to various DT bindings includes (such as clocks, resets, power domains, memory controller clients and SMMU stream IDs) for Tegra234. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmIZBZETHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoUclEACDN9W0ehB9rPOAGcgMQHrG6Eglf/sE l6faEST5sP5IWhFHCdm97NeIQAVOO7alQv2UurjT7MIdabH4fBk2ck6xdnP5eztW wDjvVy6YQc7vuQKJOdqbox1AvYRXwAYckIc3y6A9j9pR3K0AUCWMR5JeIMC7m0Um Iz67d0Bx4WTqaSNuw0zaCqbJEdeKA8pcCpkedAeWW2DL4NpctcJCzJL0QFXKOypy NuL13euaIxET//tu3Jec6acVEQrzr0ymrRPuQV4v6+rnaZy8AO/PbMUJb0XOtpwp C0j5YUkvdhq26NY52M1Z7duHADF7UHgxDuSnU9mbq71IhFtEEukhWvcJ+fLEbwSP ijsPuTJxc7pYYTdrOC+gzj+NNtqq4abiDJfowQPe/0DPqGrVbCn6GjAGzi8tf7SY 6ScI9pRQGDvrTW021/Z6y7hlH4hq38Ypir7FdmppVnFbTnjN9r35vqR3LGDTiJq3 Q3hGXeAuIg7rQowry/a+1+iy8KUOpStRAxtx9TpgYiW/4ru/ubzp8thKx1l6X9su DKoOe/Atq2QAqjO+4D+7s8LPUGYSu2OLYgAjQ6e9ZnlVDTdOHirr2OwxI5k6zOLR +m65qmRdccyUqcNvvh576l7mTf3SbGFd4C3L5RAIaFP3ltAzYrqphBtgZjT27lqj uv47eQBlPdyH9g== =IFUM -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIc19wACgkQmmx57+YA GNlrHQ//Wiax3wrw0kxbD7DnYakfbHrZLnMb6C5ffQVn3ANBt4A1xaEgpzjxikCt T5HqQrk1lP1Bo0wFIOdo2gDNR+CmtaJLv3YXn8H9CuYTdqLiSwiR0Dx3JdawWoh+ +vpBWJyIf/hqKH9Uq98iPAJQAOUSOgs5n4whw6aUMDU4GlqYK8QfXICad9KG8ug5 YY/oKXUh9czATUnnknY8eKtsna1zSbutgegVv1F4J57nYZ19NB/5+svyjMddm6IQ q45GXoxJ8Y1Sk6oO2AMcOXjoUbjdWq9ToC1NV2bVM9az28d0RHlHJRSyI5o9XkXy ImrNVCU5Lpjkchrcod6YkhAoDz6xn5jLIuH0ni0wNSKKW5aWO7IC0t1dXloj4Of5 9ibeofOoXnIbP5VC3iotQQFhLMBdn2kpbW2A/nfnyTXm/USrXwkWcMkA/xPaA1A/ wXG3qNyJDtP+0cStRy7V9b2SCFxuCnIHYqhxFEtuULnqNrlA6j1aPIeo5kIZ93Gy /ifJ9NTFId3BwSXW7vl0tLrjzlFHmo0MsN4feC/kgHc+X8URjBqWrYSqse/Yv1Zw x26Dj6bRIJj91VeKpH6DIBI9TNOgEqIY489wscyjMgkTgUWBTzKbGYxU2/X2OtGs IcGOonWuJ+3BHpmK9ImjQ2K0YUMARRm5kYf9reYhRFFi+L4icEw= =1fay -----END PGP SIGNATURE----- Merge tag 'tegra-for-5.18-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt dt-bindings: Changes for v5.18-rc1 This contains additions to various DT bindings includes (such as clocks, resets, power domains, memory controller clients and SMMU stream IDs) for Tegra234. * tag 'tegra-for-5.18-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: memory: Add Tegra234 PCIe memory dt-bindings: power: Add Tegra234 PCIe power domains dt-bindings: Add Tegra234 PCIe clocks and resets dt-bindings: Document Tegra234 HDA support dt-bindings: Add HDA support for Tegra234 dt-bindings: Add Tegra234 APE support dt-bindings: Add headers for Tegra234 PWM dt-bindings: Add headers for Tegra234 I2C Link: https://lore.kernel.org/r/20220225164741.1064416-2-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
cba4cdeb35
@ -23,6 +23,7 @@ properties:
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- const: nvidia,tegra30-hda
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- items:
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- enum:
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- nvidia,tegra234-hda
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- nvidia,tegra194-hda
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- nvidia,tegra186-hda
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- nvidia,tegra210-hda
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@ -41,9 +42,11 @@ properties:
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maxItems: 1
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clocks:
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minItems: 2
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maxItems: 3
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clock-names:
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minItems: 2
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items:
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- const: hda
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- const: hda2hdmi
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@ -1,5 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */
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/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
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#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
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#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
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@ -9,6 +9,26 @@
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* @defgroup bpmp_clock_ids Clock ID's
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* @{
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*/
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/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
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#define TEGRA234_CLK_AHUB 4U
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/** @brief output of gate CLK_ENB_APB2APE */
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#define TEGRA234_CLK_APB2APE 5U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
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#define TEGRA234_CLK_APE 6U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
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#define TEGRA234_CLK_AUD_MCLK 7U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
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#define TEGRA234_CLK_DMIC1 15U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
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#define TEGRA234_CLK_DMIC2 16U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
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#define TEGRA234_CLK_DMIC3 17U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
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#define TEGRA234_CLK_DMIC4 18U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
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#define TEGRA234_CLK_DSPK1 29U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
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#define TEGRA234_CLK_DSPK2 30U
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/**
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* @brief controls the EMC clock frequency.
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* @details Doing a clk_set_rate on this clock will select the
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@ -20,15 +40,126 @@
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#define TEGRA234_CLK_EMC 31U
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/** @brief output of gate CLK_ENB_FUSE */
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#define TEGRA234_CLK_FUSE 40U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
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#define TEGRA234_CLK_I2C1 48U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
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#define TEGRA234_CLK_I2C2 49U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
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#define TEGRA234_CLK_I2C3 50U
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/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
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#define TEGRA234_CLK_I2C4 51U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
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#define TEGRA234_CLK_I2C6 52U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
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#define TEGRA234_CLK_I2C7 53U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
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#define TEGRA234_CLK_I2C8 54U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
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#define TEGRA234_CLK_I2C9 55U
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/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
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#define TEGRA234_CLK_I2S1 56U
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/** @brief clock recovered from I2S1 input */
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#define TEGRA234_CLK_I2S1_SYNC_INPUT 57U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
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#define TEGRA234_CLK_I2S2 58U
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/** @brief clock recovered from I2S2 input */
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#define TEGRA234_CLK_I2S2_SYNC_INPUT 59U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
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#define TEGRA234_CLK_I2S3 60U
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/** @brief clock recovered from I2S3 input */
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#define TEGRA234_CLK_I2S3_SYNC_INPUT 61U
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/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
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#define TEGRA234_CLK_I2S4 62U
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/** @brief clock recovered from I2S4 input */
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#define TEGRA234_CLK_I2S4_SYNC_INPUT 63U
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/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
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#define TEGRA234_CLK_I2S5 64U
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/** @brief clock recovered from I2S5 input */
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#define TEGRA234_CLK_I2S5_SYNC_INPUT 65U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */
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#define TEGRA234_CLK_I2S6 66U
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/** @brief clock recovered from I2S6 input */
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#define TEGRA234_CLK_I2S6_SYNC_INPUT 67U
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/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
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#define TEGRA234_CLK_PLLA 93U
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/** @brief PLLP clk output */
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#define TEGRA234_CLK_PLLP_OUT0 102U
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/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
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#define TEGRA234_CLK_PLLA_OUT0 104U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
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#define TEGRA234_CLK_PWM1 105U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
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#define TEGRA234_CLK_PWM2 106U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
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#define TEGRA234_CLK_PWM3 107U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
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#define TEGRA234_CLK_PWM4 108U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
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#define TEGRA234_CLK_PWM5 109U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
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#define TEGRA234_CLK_PWM6 110U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
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#define TEGRA234_CLK_PWM7 111U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
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#define TEGRA234_CLK_PWM8 112U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
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#define TEGRA234_CLK_SDMMC4 123U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
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#define TEGRA234_CLK_SYNC_DMIC1 139U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
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#define TEGRA234_CLK_SYNC_DMIC2 140U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
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#define TEGRA234_CLK_SYNC_DMIC3 141U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
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#define TEGRA234_CLK_SYNC_DMIC4 142U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
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#define TEGRA234_CLK_SYNC_DSPK1 143U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
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#define TEGRA234_CLK_SYNC_DSPK2 144U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
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#define TEGRA234_CLK_SYNC_I2S1 145U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
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#define TEGRA234_CLK_SYNC_I2S2 146U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
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#define TEGRA234_CLK_SYNC_I2S3 147U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
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#define TEGRA234_CLK_SYNC_I2S4 148U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
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#define TEGRA234_CLK_SYNC_I2S5 149U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
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#define TEGRA234_CLK_SYNC_I2S6 150U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
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#define TEGRA234_CLK_UARTA 155U
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/** @brief output of gate CLK_ENB_PEX1_CORE_6 */
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#define TEGRA234_CLK_PEX1_C6_CORE 161U
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/** @brief output of gate CLK_ENB_PEX2_CORE_7 */
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#define TEGRA234_CLK_PEX2_C7_CORE 171U
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/** @brief output of gate CLK_ENB_PEX2_CORE_8 */
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#define TEGRA234_CLK_PEX2_C8_CORE 172U
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/** @brief output of gate CLK_ENB_PEX2_CORE_9 */
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#define TEGRA234_CLK_PEX2_C9_CORE 173U
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/** @brief output of gate CLK_ENB_PEX2_CORE_10 */
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#define TEGRA234_CLK_PEX2_C10_CORE 187U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
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#define TEGRA234_CLK_SDMMC_LEGACY_TM 219U
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/** @brief output of gate CLK_ENB_PEX0_CORE_0 */
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#define TEGRA234_CLK_PEX0_C0_CORE 220U
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/** @brief output of gate CLK_ENB_PEX0_CORE_1 */
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#define TEGRA234_CLK_PEX0_C1_CORE 221U
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/** @brief output of gate CLK_ENB_PEX0_CORE_2 */
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#define TEGRA234_CLK_PEX0_C2_CORE 222U
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/** @brief output of gate CLK_ENB_PEX0_CORE_3 */
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#define TEGRA234_CLK_PEX0_C3_CORE 223U
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/** @brief output of gate CLK_ENB_PEX0_CORE_4 */
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#define TEGRA234_CLK_PEX0_C4_CORE 224U
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/** @brief output of gate CLK_ENB_PEX1_CORE_5 */
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#define TEGRA234_CLK_PEX1_C5_CORE 225U
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/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
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#define TEGRA234_CLK_PLLC4 237U
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/** @brief 32K input clock provided by PMIC */
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#define TEGRA234_CLK_CLK_32K 289U
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/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */
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#define TEGRA234_CLK_AZA_2XBIT 457U
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/** @brief aza_2xbitclk / 2 (aza_bitclk) */
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#define TEGRA234_CLK_AZA_BIT 458U
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#endif
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@ -1,4 +1,5 @@
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
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#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H
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#define DT_BINDINGS_MEMORY_TEGRA234_MC_H
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@ -7,15 +8,59 @@
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#define TEGRA234_SID_INVALID 0x00
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#define TEGRA234_SID_PASSTHROUGH 0x7f
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/* NISO0 stream IDs */
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#define TEGRA234_SID_APE 0x02
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#define TEGRA234_SID_HDA 0x03
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#define TEGRA234_SID_PCIE0 0x12
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#define TEGRA234_SID_PCIE4 0x13
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#define TEGRA234_SID_PCIE5 0x14
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#define TEGRA234_SID_PCIE6 0x15
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#define TEGRA234_SID_PCIE9 0x1f
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/* NISO1 stream IDs */
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#define TEGRA234_SID_SDMMC4 0x02
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#define TEGRA234_SID_PCIE1 0x05
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#define TEGRA234_SID_PCIE2 0x06
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#define TEGRA234_SID_PCIE3 0x07
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#define TEGRA234_SID_PCIE7 0x08
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#define TEGRA234_SID_PCIE8 0x09
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#define TEGRA234_SID_PCIE10 0x0b
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#define TEGRA234_SID_BPMP 0x10
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/*
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* memory client IDs
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*/
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/* High-definition audio (HDA) read clients */
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#define TEGRA234_MEMORY_CLIENT_HDAR 0x15
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/* PCIE6 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28
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/* PCIE6 write clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29
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/* PCIE7 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a
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/* PCIE7 write clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30
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/* PCIE8 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32
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/* High-definition audio (HDA) write clients */
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#define TEGRA234_MEMORY_CLIENT_HDAW 0x35
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/* PCIE8 write clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b
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/* PCIE9 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c
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/* PCIE6r1 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d
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/* PCIE9 write clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e
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/* PCIE10 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f
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/* PCIE10 write clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40
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/* PCIE10r1 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48
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/* PCIE7r1 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49
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/* sdmmcd memory read client */
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#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
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/* sdmmcd memory write client */
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@ -28,5 +73,35 @@
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#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95
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/* BPMPDMA write client */
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#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96
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/* APEDMA read client */
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#define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f
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/* APEDMA write client */
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#define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0
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/* PCIE0 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8
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/* PCIE0 write clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9
|
||||
/* PCIE1 read clients */
|
||||
#define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda
|
||||
/* PCIE1 write clients */
|
||||
#define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb
|
||||
/* PCIE2 read clients */
|
||||
#define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc
|
||||
/* PCIE2 write clients */
|
||||
#define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd
|
||||
/* PCIE3 read clients */
|
||||
#define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde
|
||||
/* PCIE3 write clients */
|
||||
#define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf
|
||||
/* PCIE4 read clients */
|
||||
#define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0
|
||||
/* PCIE4 write clients */
|
||||
#define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1
|
||||
/* PCIE5 read clients */
|
||||
#define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2
|
||||
/* PCIE5 write clients */
|
||||
#define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3
|
||||
/* PCIE5r1 read clients */
|
||||
#define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef
|
||||
|
||||
#endif
|
||||
|
||||
22
include/dt-bindings/power/tegra234-powergate.h
Normal file
22
include/dt-bindings/power/tegra234-powergate.h
Normal file
@ -0,0 +1,22 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
|
||||
|
||||
#ifndef __ABI_MACH_T234_POWERGATE_T234_H_
|
||||
#define __ABI_MACH_T234_POWERGATE_T234_H_
|
||||
|
||||
#define TEGRA234_POWER_DOMAIN_AUD 2U
|
||||
#define TEGRA234_POWER_DOMAIN_DISP 3U
|
||||
#define TEGRA234_POWER_DOMAIN_PCIEX8A 5U
|
||||
#define TEGRA234_POWER_DOMAIN_PCIEX4A 6U
|
||||
#define TEGRA234_POWER_DOMAIN_PCIEX4BA 7U
|
||||
#define TEGRA234_POWER_DOMAIN_PCIEX4BB 8U
|
||||
#define TEGRA234_POWER_DOMAIN_PCIEX1A 9U
|
||||
#define TEGRA234_POWER_DOMAIN_PCIEX4CA 13U
|
||||
#define TEGRA234_POWER_DOMAIN_PCIEX4CB 14U
|
||||
#define TEGRA234_POWER_DOMAIN_PCIEX4CC 15U
|
||||
#define TEGRA234_POWER_DOMAIN_PCIEX8B 16U
|
||||
#define TEGRA234_POWER_DOMAIN_MGBEA 17U
|
||||
#define TEGRA234_POWER_DOMAIN_MGBEB 18U
|
||||
#define TEGRA234_POWER_DOMAIN_MGBEC 19U
|
||||
|
||||
#endif
|
||||
@ -1,5 +1,5 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. */
|
||||
/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
|
||||
|
||||
#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H
|
||||
#define DT_BINDINGS_RESET_TEGRA234_RESET_H
|
||||
@ -10,8 +10,51 @@
|
||||
* @brief Identifiers for Resets controllable by firmware
|
||||
* @{
|
||||
*/
|
||||
#define TEGRA234_RESET_PEX1_CORE_6 11U
|
||||
#define TEGRA234_RESET_PEX1_CORE_6_APB 12U
|
||||
#define TEGRA234_RESET_PEX1_COMMON_APB 13U
|
||||
#define TEGRA234_RESET_PEX2_CORE_7 14U
|
||||
#define TEGRA234_RESET_PEX2_CORE_7_APB 15U
|
||||
#define TEGRA234_RESET_HDA 20U
|
||||
#define TEGRA234_RESET_HDACODEC 21U
|
||||
#define TEGRA234_RESET_I2C1 24U
|
||||
#define TEGRA234_RESET_PEX2_CORE_8 25U
|
||||
#define TEGRA234_RESET_PEX2_CORE_8_APB 26U
|
||||
#define TEGRA234_RESET_PEX2_CORE_9 27U
|
||||
#define TEGRA234_RESET_PEX2_CORE_9_APB 28U
|
||||
#define TEGRA234_RESET_I2C2 29U
|
||||
#define TEGRA234_RESET_I2C3 30U
|
||||
#define TEGRA234_RESET_I2C4 31U
|
||||
#define TEGRA234_RESET_I2C6 32U
|
||||
#define TEGRA234_RESET_I2C7 33U
|
||||
#define TEGRA234_RESET_I2C8 34U
|
||||
#define TEGRA234_RESET_I2C9 35U
|
||||
#define TEGRA234_RESET_PEX2_CORE_10 56U
|
||||
#define TEGRA234_RESET_PEX2_CORE_10_APB 57U
|
||||
#define TEGRA234_RESET_PEX2_COMMON_APB 58U
|
||||
#define TEGRA234_RESET_PWM1 68U
|
||||
#define TEGRA234_RESET_PWM2 69U
|
||||
#define TEGRA234_RESET_PWM3 70U
|
||||
#define TEGRA234_RESET_PWM4 71U
|
||||
#define TEGRA234_RESET_PWM5 72U
|
||||
#define TEGRA234_RESET_PWM6 73U
|
||||
#define TEGRA234_RESET_PWM7 74U
|
||||
#define TEGRA234_RESET_PWM8 75U
|
||||
#define TEGRA234_RESET_SDMMC4 85U
|
||||
#define TEGRA234_RESET_UARTA 100U
|
||||
#define TEGRA234_RESET_PEX0_CORE_0 116U
|
||||
#define TEGRA234_RESET_PEX0_CORE_1 117U
|
||||
#define TEGRA234_RESET_PEX0_CORE_2 118U
|
||||
#define TEGRA234_RESET_PEX0_CORE_3 119U
|
||||
#define TEGRA234_RESET_PEX0_CORE_4 120U
|
||||
#define TEGRA234_RESET_PEX0_CORE_0_APB 121U
|
||||
#define TEGRA234_RESET_PEX0_CORE_1_APB 122U
|
||||
#define TEGRA234_RESET_PEX0_CORE_2_APB 123U
|
||||
#define TEGRA234_RESET_PEX0_CORE_3_APB 124U
|
||||
#define TEGRA234_RESET_PEX0_CORE_4_APB 125U
|
||||
#define TEGRA234_RESET_PEX0_COMMON_APB 126U
|
||||
#define TEGRA234_RESET_PEX1_CORE_5 129U
|
||||
#define TEGRA234_RESET_PEX1_CORE_5_APB 130U
|
||||
|
||||
/** @} */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user